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https://github.com/YosysHQ/yosys
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Added "techmap -map %{design-name}"
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397b00252d
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4 changed files with 29 additions and 10 deletions
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@ -219,6 +219,11 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
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}
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}
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RTLIL::Design::Design()
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{
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refcount_modules_ = 0;
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}
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RTLIL::Design::~Design()
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{
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for (auto it = modules_.begin(); it != modules_.end(); it++)
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@ -352,11 +352,16 @@ struct RTLIL::Design
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std::map<RTLIL::IdString, RTLIL::Selection> selection_vars;
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std::string selected_active_module;
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Design();
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~Design();
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RTLIL::ObjRange<RTLIL::Module*> modules();
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RTLIL::Module *module(RTLIL::IdString name);
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bool has(RTLIL::IdString id) const {
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return modules_.count(id) != 0;
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}
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void add(RTLIL::Module *module);
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RTLIL::Module *addModule(RTLIL::IdString name);
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void remove(RTLIL::Module *module);
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