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Using log_assert() instead of assert()

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This commit is contained in:
Clifford Wolf 2014-07-28 11:08:55 +02:00
parent d86a25f145
commit 7bd2d1064f
52 changed files with 236 additions and 251 deletions
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4
kernel/bitpattern.h
View file

@ -66,8 +66,8 @@ struct BitPatternPool
bool match(bits_t a, bits_t b)
{
assert(int(a.size()) == width);
assert(int(b.size()) == width);
log_assert(int(a.size()) == width);
log_assert(int(b.size()) == width);
for (int i = 0; i < width; i++)
if (a[i] <= RTLIL::State::S1 && b[i] <= RTLIL::State::S1 && a[i] != b[i])
return false;

1
kernel/calc.cc
View file

@ -24,7 +24,6 @@
#include "kernel/log.h"
#include "kernel/rtlil.h"
#include "libs/bigint/BigIntegerLibrary.hh"
#include <assert.h>
static void extend(RTLIL::Const &arg, int width, bool is_signed)
{

2
kernel/celltypes.h
View file

@ -313,7 +313,7 @@ struct CellTypes
return ret;
}
assert(sel.bits.size() == 0);
log_assert(sel.bits.size() == 0);
return eval(cell, arg1, arg2);
}
};

8
kernel/consteval.h
View file

@ -72,7 +72,7 @@ struct ConstEval
#ifndef NDEBUG
RTLIL::SigSpec current_val = values_map(sig);
for (int i = 0; i < SIZE(current_val); i++)
assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
#endif
values_map.add(sig, RTLIL::SigSpec(value));
}
@ -87,7 +87,7 @@ struct ConstEval
{
RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
assert(cell->has("\\Y"));
log_assert(cell->has("\\Y"));
sig_y = values_map(assign_map(cell->get("\\Y")));
if (sig_y.is_fully_const())
return true;
@ -133,7 +133,7 @@ struct ConstEval
std::vector<RTLIL::Const> y_values;
assert(y_candidates.size() > 0);
log_assert(y_candidates.size() > 0);
for (auto &yc : y_candidates) {
if (!eval(yc, undef, cell))
return false;
@ -146,7 +146,7 @@ struct ConstEval
for (size_t i = 1; i < y_values.size(); i++) {
std::vector<RTLIL::State> &slave_bits = y_values.at(i).bits;
assert(master_bits.size() == slave_bits.size());
log_assert(master_bits.size() == slave_bits.size());
for (size_t j = 0; j < master_bits.size(); j++)
if (master_bits[j] != slave_bits[j])
master_bits[j] = RTLIL::State::Sx;

2
kernel/driver.cc
View file

@ -327,7 +327,7 @@ static void shell(RTLIL::Design *design)
}
try {
assert(design->selection_stack.size() == 1);
log_assert(design->selection_stack.size() == 1);
Pass::call(design, command);
} catch (log_cmd_error_expection) {
while (design->selection_stack.size() > 1)

57
kernel/log.cc
View file

@ -18,6 +18,8 @@
*/
#include "kernel/log.h"
#include "kernel/rtlil.h"
#include "kernel/register.h"
#include "kernel/compatibility.h"
#include "backends/ilang/ilang_backend.h"
@ -29,9 +31,6 @@
#include <vector>
#include <list>
// declared extern in log.h
std::map<std::string, std::pair<std::string, int>> extra_coverage_data;
std::vector<FILE*> log_files;
FILE *log_errfile = NULL;
bool log_time = false;
@ -192,6 +191,10 @@ void log_flush()
fflush(f);
}
void log_dump_val_worker(RTLIL::SigSpec v) {
log("%s", log_signal(v));
}
const char *log_signal(const RTLIL::SigSpec &sig, bool autoint)
{
char *ptr;
@ -231,3 +234,51 @@ void log_cell(RTLIL::Cell *cell, std::string indent)
free(ptr);
}
// ---------------------------------------------------
// This is the magic behind the code coverage counters
// ---------------------------------------------------
std::map<std::string, std::pair<std::string, int>> extra_coverage_data;
void cover_extra(std::string parent, std::string id, bool increment) {
if (extra_coverage_data.count(id) == 0) {
for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++)
if (p->id == parent)
extra_coverage_data[id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
log_assert(extra_coverage_data.count(id));
}
if (increment)
extra_coverage_data[id].second++;
}
std::map<std::string, std::pair<std::string, int>> get_coverage_data()
{
std::map<std::string, std::pair<std::string, int>> coverage_data;
for (auto &it : REGISTER_INTERN::pass_register) {
std::string key = stringf("passes.%s", it.first.c_str());
coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__);
coverage_data[key].second += it.second->call_counter;
}
for (auto &it : extra_coverage_data) {
if (coverage_data.count(it.first))
log("WARNING: found duplicate coverage id \"%s\".\n", it.first.c_str());
coverage_data[it.first].first = it.second.first;
coverage_data[it.first].second += it.second.second;
}
for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) {
if (coverage_data.count(p->id))
log("WARNING: found duplicate coverage id \"%s\".\n", p->id);
coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
coverage_data[p->id].second += p->counter;
}
for (auto &it : coverage_data)
if (!it.second.first.compare(0, strlen(YOSYS_SRC "/"), YOSYS_SRC "/"))
it.second.first = it.second.first.substr(strlen(YOSYS_SRC "/"));
return coverage_data;
}

56
kernel/log.h
View file

@ -20,15 +20,15 @@
#ifndef LOG_H
#define LOG_H
#include "kernel/rtlil.h"
#include "kernel/register.h"
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <sys/time.h>
#include <sys/resource.h>
#include <map>
#include <vector>
#include <string>
#define S__LINE__sub2(x) #x
#define S__LINE__sub1(x) S__LINE__sub2(x)
@ -59,6 +59,11 @@ void log_pop();
void log_reset_stack();
void log_flush();
namespace RTLIL {
struct SigSpec;
struct Cell;
}
const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);
const char *log_id(std::string id);
@ -96,47 +101,8 @@ extern "C" struct CoverData __stop_yosys_cover_list[];
extern std::map<std::string, std::pair<std::string, int>> extra_coverage_data;
static inline void cover_extra(std::string parent, std::string id, bool increment = true) {
if (extra_coverage_data.count(id) == 0) {
for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++)
if (p->id == parent)
extra_coverage_data[id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
log_assert(extra_coverage_data.count(id));
}
if (increment)
extra_coverage_data[id].second++;
}
static inline std::map<std::string, std::pair<std::string, int>> get_coverage_data()
{
std::map<std::string, std::pair<std::string, int>> coverage_data;
for (auto &it : REGISTER_INTERN::pass_register) {
std::string key = stringf("passes.%s", it.first.c_str());
coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__);
coverage_data[key].second += it.second->call_counter;
}
for (auto &it : extra_coverage_data) {
if (coverage_data.count(it.first))
log("WARNING: found duplicate coverage id \"%s\".\n", it.first.c_str());
coverage_data[it.first].first = it.second.first;
coverage_data[it.first].second += it.second.second;
}
for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) {
if (coverage_data.count(p->id))
log("WARNING: found duplicate coverage id \"%s\".\n", p->id);
coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
coverage_data[p->id].second += p->counter;
}
for (auto &it : coverage_data)
if (!it.second.first.compare(0, strlen(YOSYS_SRC "/"), YOSYS_SRC "/"))
it.second.first = it.second.first.substr(strlen(YOSYS_SRC "/"));
return coverage_data;
}
void cover_extra(std::string parent, std::string id, bool increment = true);
std::map<std::string, std::pair<std::string, int>> get_coverage_data();
#define cover_list(_id, ...) do { cover(_id); \
std::string r = cover_list_worker(_id, __VA_ARGS__); \
@ -234,9 +200,9 @@ static inline void log_dump_val_worker(bool v) { log("%s", v ? "true" : "false")
static inline void log_dump_val_worker(double v) { log("%f", v); }
static inline void log_dump_val_worker(const char *v) { log("%s", v); }
static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); }
static inline void log_dump_val_worker(RTLIL::SigSpec v) { log("%s", log_signal(v)); }
static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); }
static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }
void log_dump_val_worker(RTLIL::SigSpec v);
template<typename T>
static inline void log_dump_val_worker(T *ptr) { log("%p", ptr); }

15
kernel/register.cc
View file

@ -20,7 +20,6 @@
#include "kernel/compatibility.h"
#include "kernel/register.h"
#include "kernel/log.h"
#include <assert.h>
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
@ -50,7 +49,7 @@ Pass::Pass(std::string name, std::string short_help) : pass_name(name), short_he
void Pass::run_register()
{
assert(pass_register.count(pass_name) == 0);
log_assert(pass_register.count(pass_name) == 0);
pass_register[pass_name] = this;
}
@ -67,7 +66,7 @@ void Pass::done_register()
frontend_register.clear();
pass_register.clear();
backend_register.clear();
assert(first_queued_pass == NULL);
log_assert(first_queued_pass == NULL);
}
Pass::~Pass()
@ -252,10 +251,10 @@ Frontend::Frontend(std::string name, std::string short_help) : Pass("read_"+name
void Frontend::run_register()
{
assert(pass_register.count(pass_name) == 0);
log_assert(pass_register.count(pass_name) == 0);
pass_register[pass_name] = this;
assert(frontend_register.count(frontend_name) == 0);
log_assert(frontend_register.count(frontend_name) == 0);
frontend_register[frontend_name] = this;
}
@ -265,7 +264,7 @@ Frontend::~Frontend()
void Frontend::execute(std::vector<std::string> args, RTLIL::Design *design)
{
assert(next_args.empty());
log_assert(next_args.empty());
do {
FILE *f = NULL;
next_args.clear();
@ -383,10 +382,10 @@ Backend::Backend(std::string name, std::string short_help) : Pass("write_"+name,
void Backend::run_register()
{
assert(pass_register.count(pass_name) == 0);
log_assert(pass_register.count(pass_name) == 0);
pass_register[pass_name] = this;
assert(backend_register.count(backend_name) == 0);
log_assert(backend_register.count(backend_name) == 0);
backend_register[backend_name] = this;
}

119
kernel/rtlil.cc
View file

@ -23,7 +23,6 @@
#include "frontends/verilog/verilog_frontend.h"
#include "backends/ilang/ilang_backend.h"
#include <assert.h>
#include <string.h>
#include <algorithm>
@ -238,15 +237,15 @@ RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
void RTLIL::Design::add(RTLIL::Module *module)
{
assert(modules_.count(module->name) == 0);
assert(refcount_modules_ == 0);
log_assert(modules_.count(module->name) == 0);
log_assert(refcount_modules_ == 0);
modules_[module->name] = module;
}
RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
{
assert(modules_.count(name) == 0);
assert(refcount_modules_ == 0);
log_assert(modules_.count(name) == 0);
log_assert(refcount_modules_ == 0);
modules_[name] = new RTLIL::Module;
modules_[name]->name = name;
return modules_[name];
@ -254,7 +253,7 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
void RTLIL::Design::remove(RTLIL::Module *module)
{
assert(modules_.at(module->name) == module);
log_assert(modules_.at(module->name) == module);
modules_.erase(module->name);
delete module;
}
@ -263,8 +262,8 @@ void RTLIL::Design::check()
{
#ifndef NDEBUG
for (auto &it : modules_) {
assert(it.first == it.second->name);
assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
log_assert(it.first == it.second->name);
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
it.second->check();
}
#endif
@ -760,57 +759,57 @@ void RTLIL::Module::check()
{
#ifndef NDEBUG
for (auto &it : wires_) {
assert(it.first == it.second->name);
assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
assert(it.second->width >= 0);
assert(it.second->port_id >= 0);
log_assert(it.first == it.second->name);
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
log_assert(it.second->width >= 0);
log_assert(it.second->port_id >= 0);
for (auto &it2 : it.second->attributes) {
assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
}
}
for (auto &it : memories) {
assert(it.first == it.second->name);
assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
assert(it.second->width >= 0);
assert(it.second->size >= 0);
log_assert(it.first == it.second->name);
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
log_assert(it.second->width >= 0);
log_assert(it.second->size >= 0);
for (auto &it2 : it.second->attributes) {
assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
}
}
for (auto &it : cells_) {
assert(it.first == it.second->name);
assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
log_assert(it.first == it.second->name);
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
for (auto &it2 : it.second->connections()) {
assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
it2.second.check();
}
for (auto &it2 : it.second->attributes) {
assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
}
for (auto &it2 : it.second->parameters) {
assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
}
InternalCellChecker checker(this, it.second);
checker.check();
}
for (auto &it : processes) {
assert(it.first == it.second->name);
assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
log_assert(it.first == it.second->name);
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
// FIXME: More checks here..
}
for (auto &it : connections_) {
assert(it.first.size() == it.second.size());
log_assert(it.first.size() == it.second.size());
it.first.check();
it.second.check();
}
for (auto &it : attributes) {
assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
}
#endif
}
@ -934,7 +933,7 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
{
assert(wires_[wire->name] == wire);
log_assert(wires_[wire->name] == wire);
log_assert(refcount_wires_ == 0);
wires_.erase(wire->name);
wire->name = new_name;
@ -943,7 +942,7 @@ void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
{
assert(cells_[cell->name] == cell);
log_assert(cells_[cell->name] == cell);
log_assert(refcount_wires_ == 0);
cells_.erase(cell->name);
cell->name = new_name;
@ -952,7 +951,7 @@ void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
{
assert(count_id(old_name) != 0);
log_assert(count_id(old_name) != 0);
if (wires_.count(old_name))
rename(wires_.at(old_name), new_name);
else if (cells_.count(old_name))
@ -1927,11 +1926,11 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
pattern.unpack();
with.unpack();
assert(other != NULL);
assert(width_ == other->width_);
log_assert(other != NULL);
log_assert(width_ == other->width_);
other->unpack();
assert(pattern.width_ == with.width_);
log_assert(pattern.width_ == with.width_);
std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
for (int i = 0; i < SIZE(pattern.bits_); i++)
@ -1966,7 +1965,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
unpack();
if (other != NULL) {
assert(width_ == other->width_);
log_assert(width_ == other->width_);
other->unpack();
}
@ -2005,7 +2004,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigS
if (other != NULL)
other->pack();
assert(other == NULL || width_ == other->width_);
log_assert(other == NULL || width_ == other->width_);
std::set<RTLIL::SigBit> pat = pattern.to_sigbit_set();
std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
@ -2033,9 +2032,9 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
unpack();
with.unpack();
assert(offset >= 0);
assert(with.width_ >= 0);
assert(offset+with.width_ <= width_);
log_assert(offset >= 0);
log_assert(with.width_ >= 0);
log_assert(offset+with.width_ <= width_);
for (int i = 0; i < with.width_; i++)
bits_.at(offset + i) = with.bits_.at(i);
@ -2085,9 +2084,9 @@ void RTLIL::SigSpec::remove(int offset, int length)
unpack();
assert(offset >= 0);
assert(length >= 0);
assert(offset + length <= width_);
log_assert(offset >= 0);
log_assert(length >= 0);
log_assert(offset + length <= width_);
bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
width_ = bits_.size();
@ -2236,28 +2235,28 @@ void RTLIL::SigSpec::check() const
const RTLIL::SigChunk chunk = chunks_[i];
if (chunk.wire == NULL) {
if (i > 0)
assert(chunks_[i-1].wire != NULL);
assert(chunk.offset == 0);
assert(chunk.data.bits.size() == (size_t)chunk.width);
log_assert(chunks_[i-1].wire != NULL);
log_assert(chunk.offset == 0);
log_assert(chunk.data.bits.size() == (size_t)chunk.width);
} else {
if (i > 0 && chunks_[i-1].wire == chunk.wire)
assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
assert(chunk.offset >= 0);
assert(chunk.width >= 0);
assert(chunk.offset + chunk.width <= chunk.wire->width);
assert(chunk.data.bits.size() == 0);
log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
log_assert(chunk.offset >= 0);
log_assert(chunk.width >= 0);
log_assert(chunk.offset + chunk.width <= chunk.wire->width);
log_assert(chunk.data.bits.size() == 0);
}
w += chunk.width;
}
assert(w == width_);
assert(bits_.empty());
log_assert(w == width_);
log_assert(bits_.empty());
}
else
{
cover("kernel.rtlil.sigspec.check.unpacked");
assert(width_ == SIZE(bits_));
assert(chunks_.empty());
log_assert(width_ == SIZE(bits_));
log_assert(chunks_.empty());
}
}
#endif
@ -2402,7 +2401,7 @@ bool RTLIL::SigSpec::as_bool() const
cover("kernel.rtlil.sigspec.as_bool");
pack();
assert(is_fully_const() && SIZE(chunks_) <= 1);
log_assert(is_fully_const() && SIZE(chunks_) <= 1);
if (width_)
return chunks_[0].data.as_bool();
return false;
@ -2413,7 +2412,7 @@ int RTLIL::SigSpec::as_int() const
cover("kernel.rtlil.sigspec.as_int");
pack();
assert(is_fully_const() && SIZE(chunks_) <= 1);
log_assert(is_fully_const() && SIZE(chunks_) <= 1);
if (width_)
return chunks_[0].data.as_int();
return 0;
@ -2441,7 +2440,7 @@ RTLIL::Const RTLIL::SigSpec::as_const() const
cover("kernel.rtlil.sigspec.as_const");
pack();
assert(is_fully_const() && SIZE(chunks_) <= 1);
log_assert(is_fully_const() && SIZE(chunks_) <= 1);
if (width_)
return chunks_[0].data;
return RTLIL::Const();
@ -2452,7 +2451,7 @@ RTLIL::Wire *RTLIL::SigSpec::as_wire() const
cover("kernel.rtlil.sigspec.as_wire");
pack();
assert(is_wire());
log_assert(is_wire());
return chunks_[0].wire;
}
@ -2461,7 +2460,7 @@ RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
cover("kernel.rtlil.sigspec.as_chunk");
pack();
assert(is_chunk());
log_assert(is_chunk());
return chunks_[0];
}
@ -2471,7 +2470,7 @@ bool RTLIL::SigSpec::match(std::string pattern) const
pack();
std::string str = as_string();
assert(pattern.size() == str.size());
log_assert(pattern.size() == str.size());
for (size_t i = 0; i < pattern.size(); i++) {
if (pattern[i] == ' ')

16
kernel/rtlil.h
View file

@ -24,8 +24,8 @@
#include <set>
#include <vector>
#include <string>
#include <assert.h>
#include "kernel/log.h"
#include <initializer_list>
// various helpers (unrelated to RTLIL)
@ -107,7 +107,7 @@ namespace RTLIL
return std::string(*this) < std::string(rhs);
}
void check() const {
assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\')));
log_assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\')));
}
};
#endif
@ -242,7 +242,7 @@ namespace RTLIL
}
inline T operator*() const {
assert(list_p != nullptr);
log_assert(list_p != nullptr);
return it->second;
}
@ -253,7 +253,7 @@ namespace RTLIL
}
inline void operator++() {
assert(list_p != nullptr);
log_assert(list_p != nullptr);
if (++it == list_p->end()) {
(*refcount_p)--;
list_p = nullptr;
@ -677,9 +677,9 @@ struct RTLIL::SigBit
SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { }
SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { }
SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { assert(wire && wire->width == 1); }
SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { assert(wire); }
SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { assert(chunk.width == 1); }
SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { log_assert(wire && wire->width == 1); }
SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { log_assert(wire); }
SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { log_assert(chunk.width == 1); }
SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { }
SigBit(const RTLIL::SigSpec &sig);
@ -856,7 +856,7 @@ inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {
}
inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
assert(sig.size() == 1 && sig.chunks().size() == 1);
log_assert(sig.size() == 1 && sig.chunks().size() == 1);
*this = SigBit(sig.chunks().front());
}

8
kernel/satgen.h
View file

@ -116,7 +116,7 @@ struct SatGen
if (timestep_rhs < 0)
timestep_rhs = timestep_lhs;
assert(lhs.size() == rhs.size());
log_assert(lhs.size() == rhs.size());
std::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);
std::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);
@ -163,14 +163,14 @@ struct SatGen
void undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)
{
assert(model_undef);
assert(vec_y.size() == vec_yy.size());
log_assert(model_undef);
log_assert(vec_y.size() == vec_yy.size());
if (vec_y.size() > vec_undef.size()) {
std::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());
std::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());
ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));
} else {
assert(vec_y.size() == vec_undef.size());
log_assert(vec_y.size() == vec_undef.size());
ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));
}
}

13
kernel/sigtools.h
View file

@ -22,7 +22,6 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include <assert.h>
#include <set>
struct SigPool
@ -67,7 +66,7 @@ struct SigPool
void expand(RTLIL::SigSpec from, RTLIL::SigSpec to)
{
assert(SIZE(from) == SIZE(to));
log_assert(SIZE(from) == SIZE(to));
for (int i = 0; i < SIZE(from); i++) {
bitDef_t bit_from(from[i]), bit_to(to[i]);
if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)
@ -304,11 +303,11 @@ struct SigMap
// internal helper function
void merge_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2)
{
assert(bit1.wire != NULL && bit2.wire != NULL);
log_assert(bit1.wire != NULL && bit2.wire != NULL);
shared_bit_data_t *bd1 = bits[bit1];
shared_bit_data_t *bd2 = bits[bit2];
assert(bd1 != NULL && bd2 != NULL);
log_assert(bd1 != NULL && bd2 != NULL);
if (bd1 == bd2)
return;
@ -333,8 +332,8 @@ struct SigMap
// internal helper function
void set_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2)
{
assert(bit1.wire != NULL);
assert(bits.count(bit1) > 0);
log_assert(bit1.wire != NULL);
log_assert(bits.count(bit1) > 0);
bits[bit1]->map_to = bit2;
}
@ -347,7 +346,7 @@ struct SigMap
void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
{
assert(SIZE(from) == SIZE(to));
log_assert(SIZE(from) == SIZE(to));
for (int i = 0; i < SIZE(from); i++)
{