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Added copy-constructor-like module->addCell(name, other) method
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parent
2bec47a404
commit
4755e14e7b
4 changed files with 17 additions and 20 deletions
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@ -782,14 +782,8 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
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for (auto &it : memories)
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new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
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for (auto &it : cells) {
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new_mod->cells[it.first] = new RTLIL::Cell;
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new_mod->cells[it.first]->name = it.second->name;
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new_mod->cells[it.first]->type = it.second->type;
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new_mod->cells[it.first]->connections = it.second->connections;
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new_mod->cells[it.first]->parameters = it.second->parameters;
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new_mod->cells[it.first]->attributes = it.second->attributes;
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}
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for (auto &it : cells)
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new_mod->addCell(it.first, it.second);
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for (auto &it : processes)
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new_mod->processes[it.first] = it.second->clone();
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@ -912,6 +906,15 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
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return cell;
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}
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RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
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{
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RTLIL::Cell *cell = addCell(name, other->type);
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cell->connections = other->connections;
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cell->parameters = other->parameters;
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cell->attributes = other->attributes;
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return cell;
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}
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#define DEF_METHOD(_func, _y_size, _type) \
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RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
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RTLIL::Cell *cell = new RTLIL::Cell; \
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@ -302,6 +302,7 @@ struct RTLIL::Module
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RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
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RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
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RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
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// The add* methods create a cell and return the created cell. All signals must exist in advance.
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