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Replaced more old SigChunk programming patterns

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This commit is contained in:
Clifford Wolf 2014-07-24 22:47:57 +02:00
parent 7a608437c6
commit 6aa792c864
17 changed files with 101 additions and 104 deletions
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10
kernel/bitpattern.h
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@ -35,10 +35,8 @@ struct BitPatternPool
if (width > 0) {
std::vector<RTLIL::State> pattern(width);
for (int i = 0; i < width; i++) {
RTLIL::SigSpec s = sig.extract(i, 1);
assert(s.chunks().size() == 1);
if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1)
pattern[i] = s.chunks()[0].data.bits[0];
if (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1)
pattern[i] = sig[i].data;
else
pattern[i] = RTLIL::State::Sa;
}
@ -59,9 +57,7 @@ struct BitPatternPool
bits_t sig2bits(RTLIL::SigSpec sig)
{
assert(sig.is_fully_const());
assert(sig.chunks().size() == 1);
bits_t bits = sig.chunks()[0].data.bits;
bits_t bits = sig.as_const().bits;
for (auto &b : bits)
if (b > RTLIL::State::S1)
b = RTLIL::State::Sa;

6
kernel/consteval.h
View file

@ -207,9 +207,9 @@ struct ConstEval
if (sig.is_fully_const())
return true;
for (size_t i = 0; i < sig.chunks().size(); i++)
if (sig.chunks()[i].wire != NULL)
undef.append(sig.chunks()[i]);
for (auto &c : sig.chunks())
if (c.wire != NULL)
undef.append(c);
return false;
}

17
kernel/rtlil.cc
View file

@ -1999,6 +1999,14 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
return true;
}
bool RTLIL::SigSpec::is_wire() const
{
cover("kernel.rtlil.sigspec.is_wire");
pack();
return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
}
bool RTLIL::SigSpec::is_fully_const() const
{
cover("kernel.rtlil.sigspec.is_fully_const");
@ -2104,6 +2112,15 @@ RTLIL::Const RTLIL::SigSpec::as_const() const
return RTLIL::Const();
}
RTLIL::Wire *RTLIL::SigSpec::as_wire() const
{
cover("kernel.rtlil.sigspec.as_wire");
pack();
assert(is_wire());
return chunks_[0].wire;
}
bool RTLIL::SigSpec::match(std::string pattern) const
{
cover("kernel.rtlil.sigspec.match");

4
kernel/rtlil.h
View file

@ -576,6 +576,7 @@ public:
bool operator ==(const RTLIL::SigSpec &other) const;
inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }
bool is_wire() const;
bool is_fully_const() const;
bool is_fully_def() const;
bool is_fully_undef() const;
@ -585,6 +586,7 @@ public:
int as_int() const;
std::string as_string() const;
RTLIL::Const as_const() const;
RTLIL::Wire *as_wire() const;
bool match(std::string pattern) const;
@ -612,7 +614,7 @@ inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {
inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
assert(sig.size() == 1 && sig.chunks().size() == 1);
*this = SigBit(sig.chunks()[0]);
*this = SigBit(sig.chunks().front());
}
struct RTLIL::CaseRule {