mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity
15506 commits 122 branches 59 tags 72 MiB
Commit graph

4511 commits

Author SHA1 Message Date
Marcelina Kościelnicka
1667ad658b opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits. 
The previous code, in addition to being needlessly limitted to 32 bits
in the first place, also had UB for the 31th bit (doing 1 << 31).
 2021-06-09 19:53:44 +02:00
Marcelina Kościelnicka
12b3a9765d opt_expr: Optimize div/mod by const 1. 
Turns out the code for div by a power of 2 is already almost capable of
optimizing this to a shift-by-0 or and-with-0, which will be further
folded into nothingness; let's beef it up to handle div by 1 as well.

Fixes #2820.
 2021-06-09 17:42:30 +02:00
Claire Xen
55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails 
Fixing old e-mail addresses and deadnames
 2021-06-09 13:22:52 +02:00
Claire Xenia Wolf
588137cd08 Fix deadname SVN links 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-06-09 12:44:37 +02:00
Claire Xenia Wolf
0ada13cbe2 Use HTTPS for website links, gatecat email 
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
 2021-06-09 12:16:56 +02:00
Zachary Snow
d9f11bb7a6 autoname: simple perf optimizations 2021-06-08 15:02:42 -04:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka
13b901bf1c memory_map: Improve start_offset handling. 
Fixes #2775.
 2021-05-31 17:45:21 +02:00
Marcelina Kościelnicka
82f5829aba memory_share: Add read port merging. 
This is mostly meant for wide port recognition, but may also happen to
merge some ports with compatible initial/reset values (eg. 0 vs x).
 2021-05-29 16:05:58 +02:00
Marcelina Kościelnicka
2d10caabbc memory_share: Improve sat-based port sharing. 2021-05-28 14:25:33 +02:00
Marcelina Kościelnicka
cbf6b719fe Make a few passes auto-call Mem::narrow instead of rejecting wide ports. 
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
 2021-05-28 00:40:56 +02:00
Marcelina Kościelnicka
1eae6025e7 memory_share: Improve same-address merging, recognize wide write ports. 2021-05-27 15:53:12 +02:00
Marcelina Kościelnicka
83a218141c kernel/mem: Add sub_addr helpers. 2021-05-26 03:34:02 +02:00
Marcelina Kościelnicka
d99fce3bc7 mem/extract_rdff: Fix "no FF made" edge case. 
When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return.  Handle this case correctly in
the helper and in its users.
 2021-05-25 23:42:31 +02:00
Marcelina Kościelnicka
18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg. 
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
 2021-05-25 22:42:03 +02:00
Marcelina Kościelnicka
e6b078d156 opt_mem: Add reset/init value support. 2021-05-25 20:06:00 +02:00
Marcelina Kościelnicka
96c7d60304 memory_bram: Respect write port priority. 2021-05-25 16:28:33 +02:00
Marcelina Kościelnicka
5628f5a88f opt_mem_feedback: Respect write port priority. 2021-05-25 15:59:41 +02:00
Marcelina Kościelnicka
e0736c1622 Add memory_narrow pass. 2021-05-25 03:04:13 +02:00
Marcelina Kościelnicka
47f958ce45 memory_share: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
9d5d5a48b1 opt_mem_feedback: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
c1a4730739 memory_map: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
1c903d3e47 sim: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
69bf5c81c7 Reject wide ports in some passes that will never support them. 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka
835688bf80 opt_mem_feedback: Rewrite feedback path finding logic. 
Fixes #2766.
 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka
b706adb809 opt_mem_feedback: Convert to Mem helpers. 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka
df2b79ca76 memory_share: Use Mem helpers. 2021-05-23 23:16:12 +02:00
Marcelina Kościelnicka
afd5366fc2 extract_rdff: Add initvals parameter. 
This is not used yet, but will be needed when read port reset/initial
value support lands.
 2021-05-23 22:05:26 +02:00
Marcelina Kościelnicka
d905990d01 memory_share: Split off feedback path finding as a separate pass. 
memory_share is actually three passes in a trenchcoat.  Split off the
one that has the least in common with the other two as a separate pass.
 2021-05-23 18:30:39 +02:00
Marcelina Kościelnicka
1eea06bcc0 Add new helper class for merging FFs into cells, use for memory_dff. 
Fixes #1854.
 2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka
a23d9409e7 opt_mem: Remove write ports with const-0 EN. 
Fixes #2765.
 2021-05-23 14:30:56 +02:00
Marcelina Kościelnicka
039f4f48d5 memory_memx: Use Mem helper. 2021-05-22 22:31:07 +02:00
Marcelina Kościelnicka
c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types. 
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
 2021-05-22 21:43:00 +02:00
Marcelina Kościelnicka
8c734e07b8 memory_dff: Use Mem helper. 2021-05-21 02:26:27 +02:00
Marcelina Kościelnicka
a6081b46ce connect: Add -assert option, fix non-working sigmap. 
Should be useful for writing tests.
 2021-05-08 15:49:41 +02:00
Marcelina Kościelnicka
5c1e6a0e20 opt_dff: Fix NOT gates wired in reverse. 2021-05-04 21:03:40 +02:00
whitequark
c5c57e3f5e flatten: rewrite memid in memwr actions. 2021-04-09 09:46:53 +00:00
Marcelina Kościelnicka
b7ea71e6e3 equiv: Suggest running async2sync or clk2fflogic where appropriate. 
See #2713.
 2021-03-30 18:20:21 +02:00
Eddie Hung
8c5f379435
abc9: uniquify blackboxes like whiteboxes (#2695) 
* abc9_ops: uniquify blackboxes too

* abc9_ops: update comment

* abc9_ops: allow bypass for param-less blackboxes

* Add tests
 2021-03-29 22:02:06 -07:00
Eddie Hung
55dc5a4e4f
abc9: fix SCC issues (#2694) 
* xilinx: add SCC test for DSP48E1

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

* abc9 to break SCCs using $__ABC9_SCC_BREAKER module

* Add test

* abc9_ops: remove refs to (* abc9_keep *) on wires

* abc9_ops: do not bypass cells in an SCC

* Add myself to CODEOWNERS for abc9*

* Fix compile

* abc9_ops: run -prep_hier before scc

* Fix tests

* Remove bug reference pending fix

* abc9: fix for -prep_hier -dff

* xaiger: restore PI handling

* abc9_ops: -prep_xaiger sigmap

* abc9_ops: -mark_scc -> -break_scc

* abc9: eliminate hard-coded abc9.box from tests

Also tidy up

* Address review
 2021-03-29 22:01:57 -07:00
Iris Johnson
4c39189b13
Clarify bugpoint documentation regarding output 
Bugpoint's current documentation does specify that the result of a run is stored as the current design,
however it's easy to skim over what that means in practice. 

Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save
the reduced design.
 2021-03-24 16:24:33 -05:00
Zachary Snow
c8b45a4a82 bugpoint: add runner option 2021-03-17 15:54:00 -04:00
gatecat
dd6d34f461 blackbox: Include whiteboxed modules 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-17 13:58:04 +00:00
Marcelina Kościelnicka
a55bf6375b proc_arst: Add special-casing of clock signal in conditionals. 
The already-existing special case for conditionals on clock has been
remade as follows:

- now triggered for the last remaining edge trigger after all others
  have been converted to async reset, not just when there is only one
  sync rule in the first place
- does not require all contained assignments to be constant, as opposed
  to a reset conditional — merely const-folds the condition

In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).

Fixes #2656.
 2021-03-15 17:17:29 +01:00
Marcelina Kościelnicka
3af871f969 opt_clean: Remove init attribute bits together with removed DFFs. 
Fixes #2546.
 2021-03-15 17:16:53 +01:00
Miodrag Milanovic
81c2b92bb4 Add _pm.h files to GENLIST, fixes vcxsrc target 2021-03-11 15:56:32 +01:00
Marcelina Kościelnicka
a3528649c8 memory_dff: Remove now-useless write port handling. 2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka
4e03865d5b Add support for memory writes in processes. 2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka
c00a29296c sim: Avoid a crash on empty cell connection. 
Fixes #2513.
 2021-03-08 17:03:31 +01:00
Marcelina Kościelnicka
760284033d proc_dff: Fix emitted FF when a register is not assigned in async reset 
Fixes #2619.
 2021-03-08 17:01:43 +01:00