mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 17:15:33 +00:00
Add new helper class for merging FFs into cells, use for memory_dff.
Fixes #1854.
This commit is contained in:
Marcelina Kościelnicka
parent
a23d9409e7
commit
1eea06bcc0
7 changed files with 600 additions and 244 deletions
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@ -17,11 +17,12 @@
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*
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*/
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#include <algorithm>
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/mem.h"
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#include "kernel/ff.h"
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#include "kernel/ffmerge.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -30,185 +31,13 @@ struct MemoryDffWorker
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{
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Module *module;
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SigMap sigmap;
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vector<Cell*> dff_cells;
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dict<SigBit, SigBit> invbits;
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dict<SigBit, int> sigbit_users_count;
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FfInitVals initvals;
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FfMergeHelper merger;
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MemoryDffWorker(Module *module) : module(module), sigmap(module)
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{
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initvals.set(&sigmap, module);
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}
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bool find_sig_before_dff(RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity)
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{
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sigmap.apply(sig);
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dict<SigBit, SigBit> cache;
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for (auto &bit : sig)
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{
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if (cache.count(bit)) {
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bit = cache[bit];
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continue;
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}
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if (bit.wire == NULL)
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continue;
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if (initvals(bit) != State::Sx)
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return false;
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for (auto cell : dff_cells)
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{
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SigSpec this_clk = cell->getPort(ID::CLK);
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bool this_clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
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if (invbits.count(this_clk)) {
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this_clk = invbits.at(this_clk);
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this_clk_polarity = !this_clk_polarity;
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}
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if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
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if (this_clk != clk)
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continue;
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if (this_clk_polarity != clk_polarity)
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continue;
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}
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RTLIL::SigSpec q_norm = cell->getPort(ID::Q);
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sigmap.apply(q_norm);
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RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(ID::D));
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if (d.size() != 1)
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continue;
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if (cell->type == ID($sdffce)) {
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SigSpec rval = cell->parameters[ID::SRST_VALUE];
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SigSpec rbit = q_norm.extract(bit, &rval);
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if (cell->parameters[ID::SRST_POLARITY].as_bool())
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d = module->Mux(NEW_ID, d, rbit, cell->getPort(ID::SRST));
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else
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d = module->Mux(NEW_ID, rbit, d, cell->getPort(ID::SRST));
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}
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if (cell->type.in(ID($dffe), ID($sdffe), ID($sdffce))) {
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if (cell->parameters[ID::EN_POLARITY].as_bool())
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d = module->Mux(NEW_ID, bit, d, cell->getPort(ID::EN));
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else
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d = module->Mux(NEW_ID, d, bit, cell->getPort(ID::EN));
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}
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if (cell->type.in(ID($sdff), ID($sdffe))) {
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SigSpec rval = cell->parameters[ID::SRST_VALUE];
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SigSpec rbit = q_norm.extract(bit, &rval);
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if (cell->parameters[ID::SRST_POLARITY].as_bool())
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d = module->Mux(NEW_ID, d, rbit, cell->getPort(ID::SRST));
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else
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d = module->Mux(NEW_ID, rbit, d, cell->getPort(ID::SRST));
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}
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cache[bit] = d;
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bit = d;
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clk = this_clk;
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clk_polarity = this_clk_polarity;
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goto replaced_this_bit;
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}
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return false;
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replaced_this_bit:;
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}
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return true;
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}
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bool find_sig_after_dffe(RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, RTLIL::SigSpec &en, bool &en_polarity)
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{
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sigmap.apply(sig);
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for (auto &bit : sig)
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{
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if (bit.wire == NULL)
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continue;
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for (auto cell : dff_cells)
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{
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if (!cell->type.in(ID($dff), ID($dffe)))
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continue;
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SigSpec this_clk = cell->getPort(ID::CLK);
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bool this_clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
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SigSpec this_en = State::S1;
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bool this_en_polarity = true;
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if (cell->type == ID($dffe)) {
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this_en = cell->getPort(ID::EN);
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this_en_polarity = cell->parameters[ID::EN_POLARITY].as_bool();
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}
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if (invbits.count(this_clk)) {
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this_clk = invbits.at(this_clk);
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this_clk_polarity = !this_clk_polarity;
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}
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if (invbits.count(this_en)) {
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this_en = invbits.at(this_en);
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this_en_polarity = !this_en_polarity;
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}
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if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
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if (this_clk != clk)
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continue;
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if (this_clk_polarity != clk_polarity)
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continue;
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if (this_en != en)
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continue;
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if (this_en_polarity != en_polarity)
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continue;
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}
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RTLIL::SigSpec q_norm = cell->getPort(ID::D);
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sigmap.apply(q_norm);
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RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(ID::Q));
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if (d.size() != 1)
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continue;
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if (initvals(d) != State::Sx)
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return false;
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bit = d;
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clk = this_clk;
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clk_polarity = this_clk_polarity;
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en = this_en;
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en_polarity = this_en_polarity;
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goto replaced_this_bit;
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}
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return false;
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replaced_this_bit:;
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}
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return true;
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}
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void disconnect_dff(RTLIL::SigSpec sig)
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{
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sigmap.apply(sig);
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sig.sort_and_unify();
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std::stringstream sstr;
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sstr << "$memory_dff_disconnected$" << (autoidx++);
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RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
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for (auto cell : module->cells())
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if (cell->type.in(ID($dff), ID($dffe))) {
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RTLIL::SigSpec new_q = cell->getPort(ID::Q);
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new_q.replace(sig, new_sig);
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cell->setPort(ID::Q, new_q);
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}
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merger.set(&initvals, module);
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}
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void handle_rd_port(Mem &mem, int idx)
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@ -216,86 +45,124 @@ struct MemoryDffWorker
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auto &port = mem.rd_ports[idx];
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log("Checking read port `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str());
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bool clk_polarity = 0;
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bool en_polarity = 0;
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RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
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RTLIL::SigSpec en_data;
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RTLIL::SigSpec sig_data = port.data;
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for (auto bit : sigmap(sig_data))
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if (sigbit_users_count[bit] > 1)
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goto skip_ff_after_read_merging;
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if (find_sig_after_dffe(sig_data, clk_data, clk_polarity, en_data, en_polarity) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
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{
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if (!en_polarity)
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en_data = module->LogicNot(NEW_ID, en_data);
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disconnect_dff(sig_data);
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port.clk = clk_data;
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port.en = en_data;
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port.data = sig_data;
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port.clk_enable = true;
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port.clk_polarity = clk_polarity;
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port.transparent = false;
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mem.emit();
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log("merged data $dff to cell.\n");
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FfData ff;
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pool<std::pair<Cell *, int>> bits;
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if (!merger.find_output_ff(port.data, ff, bits)) {
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log("no output FF found.\n");
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return;
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}
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skip_ff_after_read_merging:;
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RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
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RTLIL::SigSpec sig_addr = port.addr;
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if (find_sig_before_dff(sig_addr, clk_addr, clk_polarity) &&
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clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
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{
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port.clk = clk_addr;
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if (!ff.has_clk) {
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log("output latches are not supported.\n");
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return;
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}
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if (ff.has_sr) {
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// Latches and FFs with SR are not supported.
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log("output FF has both set and reset, not supported.\n");
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return;
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}
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if (ff.has_srst || ff.has_arst || !ff.val_init.is_fully_undef()) {
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// TODO: not supported yet
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log("output FF has reset and/or init value, not supported yet.\n");
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return;
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}
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merger.remove_output_ff(bits);
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if (ff.has_en && !ff.pol_en)
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ff.sig_en = module->LogicNot(NEW_ID, ff.sig_en);
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if (ff.has_arst && !ff.pol_arst)
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ff.sig_arst = module->LogicNot(NEW_ID, ff.sig_arst);
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if (ff.has_srst && !ff.pol_srst)
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ff.sig_srst = module->LogicNot(NEW_ID, ff.sig_srst);
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port.clk = ff.sig_clk;
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port.clk_enable = true;
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port.clk_polarity = ff.pol_clk;
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if (ff.has_en)
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port.en = ff.sig_en;
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else
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port.en = State::S1;
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port.addr = sig_addr;
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port.clk_enable = true;
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port.clk_polarity = clk_polarity;
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port.transparent = true;
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mem.emit();
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log("merged address $dff to cell.\n");
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#if 0
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if (ff.has_arst) {
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port.arst = ff.sig_arst;
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port.arst_value = ff.val_arst;
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} else {
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port.arst = State::S0;
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}
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if (ff.has_srst) {
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port.srst = ff.sig_srst;
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port.srst_value = ff.val_srst;
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port.ce_over_srst = ff.ce_over_srst;
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} else {
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port.srst = State::S0;
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}
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port.init_value = ff.val_init;
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#endif
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port.data = ff.sig_q;
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mem.emit();
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log("merged output FF to cell.\n");
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}
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void handle_rd_port_addr(Mem &mem, int idx)
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{
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auto &port = mem.rd_ports[idx];
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log("Checking read port address `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str());
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FfData ff;
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pool<std::pair<Cell *, int>> bits;
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if (!merger.find_input_ff(port.addr, ff, bits)) {
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log("no address FF found.\n");
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return;
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}
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log("no (compatible) $dff found.\n");
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if (!ff.has_clk) {
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log("address latches are not supported.\n");
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return;
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}
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if (ff.has_sr || ff.has_arst) {
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log("address FF has async set and/or reset, not supported.\n");
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return;
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}
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// Trick part: this transform is invalid if the initial
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// value of the FF is fully-defined. However, we
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// cannot simply reject FFs with any defined init bit,
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// as this is often the result of merging a const bit.
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if (ff.val_init.is_fully_def()) {
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log("address FF has fully-defined init value, not supported.\n");
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return;
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}
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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auto &wport = mem.wr_ports[i];
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if (!wport.clk_enable || wport.clk != ff.sig_clk || wport.clk_polarity != ff.pol_clk) {
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log("address FF clock is not compatible with write clock.\n");
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return;
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}
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}
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// Now we're commited to merge it.
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merger.mark_input_ff(bits);
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// If the address FF has enable and/or sync reset, unmap it.
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ff.unmap_ce_srst(module);
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port.clk = ff.sig_clk;
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port.en = State::S1;
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port.addr = ff.sig_d;
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port.clk_enable = true;
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port.clk_polarity = ff.pol_clk;
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port.transparent = true;
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mem.emit();
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log("merged address FF to cell.\n");
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}
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void run()
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{
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for (auto wire : module->wires()) {
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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sigbit_users_count[bit]++;
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}
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)))
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dff_cells.push_back(cell);
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if (cell->type.in(ID($not), ID($_NOT_)) || (cell->type == ID($logic_not) && GetSize(cell->getPort(ID::A)) == 1)) {
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SigSpec sig_a = cell->getPort(ID::A);
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SigSpec sig_y = cell->getPort(ID::Y);
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if (cell->type == ID($not))
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sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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if (cell->type == ID($logic_not))
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sig_y.extend_u0(1);
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for (int i = 0; i < GetSize(sig_y); i++)
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invbits[sig_y[i]] = sig_a[i];
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}
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for (auto &conn : cell->connections())
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if (!cell->known() || cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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sigbit_users_count[bit]++;
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}
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for (auto &mem : Mem::get_selected_memories(module)) {
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std::vector<Mem> memories = Mem::get_selected_memories(module);
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for (auto &mem : memories) {
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for (int i = 0; i < GetSize(mem.rd_ports); i++) {
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if (!mem.rd_ports[i].clk_enable)
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handle_rd_port(mem, i);
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}
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}
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for (auto &mem : memories) {
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for (int i = 0; i < GetSize(mem.rd_ports); i++) {
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if (!mem.rd_ports[i].clk_enable)
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handle_rd_port_addr(mem, i);
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}
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}
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}
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};
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