mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 17:15:33 +00:00
Reject wide ports in some passes that will never support them.
This commit is contained in:
parent
35ee774ea8
commit
69bf5c81c7
4 changed files with 35 additions and 2 deletions
|
@ -1057,6 +1057,20 @@ void handle_memory(Mem &mem, const rules_t &rules)
|
|||
log(" %s=%d", it.first.c_str(), it.second);
|
||||
log("\n");
|
||||
|
||||
for (auto &port : mem.rd_ports) {
|
||||
if (port.wide_log2) {
|
||||
log("Wide read ports are not supported, skipping.\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
for (auto &port : mem.wr_ports) {
|
||||
if (port.wide_log2) {
|
||||
log("Wide write ports are not supported, skipping.\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
pool<pair<IdString, int>> failed_brams;
|
||||
dict<pair<int, int>, tuple<int, int, int>> best_rule_cache;
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue