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Code Activity
yosys/passes
History
Marcelina Kościelnicka 9d5d5a48b1 opt_mem_feedback: Add wide port support.
2021-05-25 02:57:32 +02:00
..
cmds kernel/rtlil: Extract some helpers for checking memory cell types. 2021-05-22 21:43:00 +02:00
equiv equiv: Suggest running async2sync or clk2fflogic where appropriate. 2021-03-30 18:20:21 +02:00
fsm Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
hierarchy Sign extend port connections where necessary 2020-12-18 20:33:14 -07:00
memory memory_map: Add wide port support. 2021-05-25 02:57:32 +02:00
opt opt_mem_feedback: Add wide port support. 2021-05-25 02:57:32 +02:00
pmgen Add _pm.h files to GENLIST, fixes vcxsrc target 2021-03-11 15:56:32 +01:00
proc proc_arst: Add special-casing of clock signal in conditionals. 2021-03-15 17:17:29 +01:00
sat sim: Add wide port support. 2021-05-25 02:57:32 +02:00
techmap kernel/rtlil: Extract some helpers for checking memory cell types. 2021-05-22 21:43:00 +02:00
tests Replace "ILANG" with "RTLIL" everywhere. 2020-08-26 17:29:32 +00:00