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Code Activity
14669 commits 122 branches 59 tags 72 MiB
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1952 commits

Author SHA1 Message Date
Eddie Hung
49e64ad492 test: update opt_expr_alu test 2020-05-08 11:12:58 -07:00
Eddie Hung
495acf9815 tests: opt_expr tests that depend on consumex 2020-05-08 11:07:11 -07:00
Peter Crozier
0b6b47ca67 Implement SV structs. 2020-05-08 14:40:49 +01:00
Dan Ravensloft
5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
 2020-05-07 21:03:13 +02:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990 
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
 2020-05-07 18:11:48 +02:00
Eddie Hung
a299e606f8
Merge pull request #2028 from zachjs/master 
verilog: allow null gen-if then block
 2020-05-06 12:10:28 -07:00
Zachary Snow
8f9bba1bbf verilog: allow null gen-if then block 2020-05-06 08:43:02 -04:00
Eddie Hung
004999218f techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
Eddie Hung
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src 
verilog: set src attribute for primitives
 2020-05-05 06:49:18 -07:00
whitequark
66d0ed2bcc ast/simplify: don't bitblast async ROMs declared as logic. 
Fixes #2020.
 2020-05-05 04:16:59 +00:00
Eddie Hung
2e911bc806 test: add failing test 2020-05-04 12:18:02 -07:00
Eddie Hung
eb5eb60fd4 verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
Eddie Hung
ad8e7878f6 tests: add tests for primitives' src 2020-05-04 10:21:47 -07:00
Claire Wolf
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu 
Fix the other "opt_expr -fine" bug introduced in 213a89558
 2020-05-03 11:56:29 +02:00
Eddie Hung
db13852ed6 test: add test for #2014 2020-05-02 14:22:37 -07:00
Eddie Hung
2e78daf1ca tests: aiger test for wire->start_offset != 0 2020-05-02 10:00:32 -07:00
Claire Wolf
f38d76efbf Bugfix in partsel.v signed indices test cases 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Claire Wolf
749c2ff84a Add tests based on the test case from #1990 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00
Eddie Hung
7f9ecddb7f Add testcase for #2010 2020-05-01 14:07:33 -07:00
Eddie Hung
7f203cb019 tests: fsm to use a randomly-generated seed 2020-04-24 14:31:33 -07:00
Eddie Hung
b5f38f8342 opt_expr: const_xnor replacement to pad Y with 1'b1 2020-04-24 14:13:45 -07:00
Eddie Hung
ebd6fa945d tests: opt_expr update xnor/xor tests 2020-04-24 11:16:25 -07:00
Eddie Hung
90b71eb84b opt_expr: do not group by X, more fixes 2020-04-23 18:15:07 -07:00
Eddie Hung
b84415094c tests: add opt_expr tests 2020-04-23 15:58:36 -07:00
Dan Ravensloft
3d149aff73 intel_alm: work around a Quartus ICE 2020-04-23 11:03:28 +02:00
Eddie Hung
988d47af85 tests: read +/xilinx/cell_sim.v before xilinx_dsp test 2020-04-22 17:50:30 -07:00
Eddie Hung
db09e96dff test: ice40_dsp test to read +/ice40/cells_sim.v for default params 2020-04-22 16:35:35 -07:00
Eddie Hung
f582eb14af xilinx: xilinx_dffopt to read cells_sim.v; fix test 2020-04-22 16:25:23 -07:00
Eddie Hung
fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox 
select: do not select inside black-/white- boxes unless '=' prefix used
 2020-04-22 15:35:05 -07:00
Eddie Hung
db27f2f378
Merge pull request #1973 from YosysHQ/eddie/fix1966 
tests: fix various/plugin.sh when PREFIX != /usr/local/share
 2020-04-22 10:19:30 -07:00
Eddie Hung
281cd10717 tests: update select black/white-box tests 2020-04-22 10:16:14 -07:00
Eddie Hung
28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import 
design: -import to not count black/white-boxes as candidates for top
 2020-04-22 09:32:13 -07:00
Eddie Hung
634b5e2d9f tests: use yosys-config --datdir instead of hard-coded 2020-04-22 08:29:45 -07:00
Claire Wolf
c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const 
sim: Fix handling of constant-connected cell inputs at startup
 2020-04-22 16:57:34 +02:00
Marcelina Kościelnicka
846c79b312 hierarchy: Convert positional parameters to named. 
Fixes #1821.
 2020-04-21 19:09:00 +02:00
Claire Wolf
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite 
Improved rewrite code for writing to bit slice
 2020-04-21 18:46:52 +02:00
David Shah
abf81c7639 sim: Fix handling of constant-connected cell inputs at startup 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-21 08:58:52 +01:00
Eddie Hung
38ee59184c tests: remove write_ilang 2020-04-20 15:42:29 -07:00
Eddie Hung
caf4071c8b Remove '-ignore_unknown_cells' option from 'sat' 2020-04-20 11:58:23 -07:00
Eddie Hung
a1573058e9 Simplify test case script 2020-04-20 11:54:10 -07:00
Eddie Hung
99a0958601 Remove ununsed files 2020-04-20 11:53:48 -07:00
diego
22f440506b Modifications of tests as per Eddie's request 2020-04-20 12:45:35 -05:00
Eddie Hung
34d8ff8b56 abc9: add testcase reduced from #1970 2020-04-20 09:38:29 -07:00
diego
50581d5a94 Wrong fixed value 2020-04-17 10:15:22 -05:00
Eddie Hung
9eace8f360 design: add test 2020-04-16 12:48:40 -07:00
Eddie Hung
2ddfb61e65 select: add test for not selecting inside black/white boxes 2020-04-16 12:45:04 -07:00
diego
87910732f1 Adding tests for dynamic part select optimisation 2020-04-16 13:31:05 -05:00
Eddie Hung
2623e335cc tests: add select -unset tests 2020-04-16 10:51:58 -07:00
Eddie Hung
e8a841467f tests: add design -delete tests 2020-04-16 08:05:18 -07:00
David Shah
2b57c06360
Merge pull request #1943 from YosysHQ/dave/fix-1919 
ast: Fix handling of identifiers in the global scope
 2020-04-16 13:48:20 +01:00