Claire Wolf 9e1afde7a0 Merge pull request #1851 from YosysHQ/claire/bitselwrite ... Improved rewrite code for writing to bit slice		2020-04-21 18:46:52 +02:00
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aiger	tests/aiger: Add missing .gitignore	2020-02-15 19:52:21 +01:00
arch	tests: remove write_ilang	2020-04-20 15:42:29 -07:00
asicworld
bram
errors
fsm
hana
liberty
lut
memfile	Added 'set -e' into tests/memfile/run-test.sh	2020-02-06 10:45:40 -03:00
memories
opt	opt_expr: Fix X and CO outputs for $alu identity-mapping rules.	2020-04-16 11:48:29 +02:00
opt_share
proc
realmath
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat	Merge pull request #1638 from YosysHQ/eddie/fix1631	2020-02-05 19:31:18 +01:00
select	tests: add select -unset tests	2020-04-16 10:51:58 -07:00
share
simple	Add dynamic slicing Verilog testcase	2020-03-31 11:51:31 -07:00
simple_abc9	Update simple_abc9 tests	2020-02-27 10:17:29 -08:00
smv
sva
svinterfaces
svtypes	support using previously declared types/localparams/params in package	2020-04-07 00:38:15 -04:00
techmap	tests: zinit for new types	2020-04-14 13:08:37 -07:00
tools
unit
various	Merge pull request #1851 from YosysHQ/claire/bitselwrite	2020-04-21 18:46:52 +02:00
vloghtb