mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

sim: Fix handling of constant-connected cell inputs at startup

Browse source 
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-04-21 08:58:52 +01:00
parent c98cde8842
commit abf81c7639
2 changed files with 18 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

13
tests/various/sim_const.ys Normal file
View file

@ -0,0 +1,13 @@
read_verilog <<EOT
module top(input clk, output reg [1:0] q);
wire [1:0] x = 2'b10;
always @(posedge clk)
q <= x & 2'b11;
endmodule
EOT
proc
sim -clock clk -n 1 -w top
select -assert-count 1 a:init=2'b10 top/q %i