2021 commits

Author	SHA1	Message	Date
Akash Levy	4e45a86e12	Merge branch 'YosysHQ:main' into main	2025-02-06 12:29:43 -08:00
Jannis Harder	40c690b030	extract_fa: Add test case	2025-01-30 18:45:06 +01:00
Akash Levy	2ae7490adf	Disable Verific blackbox checks (different from our preferred approach)	2025-01-21 05:46:40 -08:00
Akash Levy	bca65ceff7	opt_clean was removing the unused bits annotation	2025-01-16 19:48:31 -08:00
Akash Levy	ab338b33cb	Use equiv_opt -nocells to ensure everything is ok since dffs retain their name	2025-01-16 19:40:18 -08:00
Akash Levy	67a93dc76d	scopeinfo inverted	2025-01-16 19:36:42 -08:00
Akash Levy	90f980eb66	Changed boolopt naming	2025-01-16 19:36:27 -08:00
Akash Levy	53ed83fcac	Rename verific to import in tests and update README explanation	2025-01-16 19:34:02 -08:00
Alain Dargelas	84c6be1edd	Add splitfanout tests	2025-01-16 12:04:53 -08:00
Alain Dargelas	31a5197a1c	muxadd and muldiv_c peepopt	2025-01-15 16:57:19 -08:00
Akash Levy	5c514e00a4	Sync with upstream	2025-01-13 17:20:59 -08:00
N. Engelhardt	7e3990b681	Merge pull request #4837 from YosysHQ/json_scopinfo_opt ... write_json: add option to include $scopeinfo cells	2025-01-10 09:57:22 +00:00
N. Engelhardt	77b28442a5	emit $scopeinfo cells by default	2025-01-08 14:47:46 +01:00
Martin Povišer	ca0ace66bc	Merge pull request #4817 from povik/macc_v2-1 ... macc: Stop using the B port	2025-01-08 14:42:51 +01:00
N. Engelhardt	dab7905cbe	write_json: add option to include $scopeinfo cells	2025-01-08 13:33:56 +01:00
Martin Povišer	652a1b9806	macc: Stop using the B port ... The B port is for single-bit summands. These can just as well be represented as an additional summand on the A port (which supports summands of arbitrary width). An upcoming `$macc_v2` cell won't be special-casing single-bit summands in any way. In preparation, make the following changes: * remove the `bit_ports` field from the `Macc` helper (instead add any single-bit summands to `ports` next to other summands) * leave `B` empty on cells emitted from `Macc::to_cell`	2025-01-08 13:03:35 +01:00
Akash Levy	443613da69	Merge branch 'YosysHQ:main' into main	2025-01-07 00:56:19 -05:00
Martin Povišer	41e4aa8f0a	Merge pull request #4819 from povik/wreduce-resign ... wreduce: Optimize signedness when possible	2025-01-06 15:27:55 +01:00
Akash Levy	1dcf75d175	Sync	2024-12-19 21:40:30 -08:00
Emil J	6ab5be4a0e	Merge pull request #4814 from YosysHQ/emil/make-test-fasterer ... test: every test everywhere all at once	2024-12-18 19:02:39 +01:00
Martin Povišer	08778917db	wreduce: Optimize signedness when possible	2024-12-16 12:57:08 +01:00
Emil J. Tywoniak	6240aec433	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
Akash Levy	1242db626f	Merge remote-tracking branch 'upstream/main'	2024-12-12 22:49:19 -08:00
N. Engelhardt	378864d33b	bound attributes: handle vhdl null ranges	2024-12-12 11:42:39 +01:00
Emil J. Tywoniak	603e5eb30a	test: every test everywhere all at once	2024-12-12 01:28:36 +01:00
Akash Levy	caaef5ac14	Merge branch 'YosysHQ:main' into main	2024-12-11 12:00:34 -08:00
N. Engelhardt	03033ab6d4	add more tests for bounds attributes, fix attributes appearing in verilog	2024-12-11 16:11:02 +01:00
Martin Povišer	4bd6061709	Merge pull request #4799 from povik/wrapcell-unused ... wrapcell: Optionally track unused outputs	2024-12-10 21:16:28 +01:00
Emil J. Tywoniak	55dcf0e200	tests: fix dfflibmap test - false negative conflict multiple -liberty vs enable inference	2024-12-10 15:48:23 +01:00
Martin Povišer	48c8d70a45	wrapcell: Test check -assert post wrapping	2024-12-10 15:13:31 +01:00
Emil J	87736a2bf9	Merge pull request #4807 from YosysHQ/emil/dfflibmap-test-dffe ... dfflibmap: cover enable inference with test	2024-12-10 12:41:11 +01:00
Akash Levy	e0ba08dd1d	Merge branch 'YosysHQ:main' into main	2024-12-09 11:13:47 -08:00
Martin Povišer	b0708a38bf	Merge pull request #4678 from povik/tcl-rtlil-api ... Start Tcl design inspection methods	2024-12-09 15:44:58 +01:00
Emil J. Tywoniak	681b678417	dfflibmap: cover enable inference with test	2024-12-09 14:18:08 +01:00
Akash Levy	8bb193d7c5	Merge branch 'YosysHQ:main' into main	2024-12-08 15:44:46 -08:00
Miodrag Milanovic	05398889ad	Add verific verilog test cases for blackboxes	2024-12-06 16:13:25 +01:00
N. Engelhardt	8b0f665cc5	add setenv pass	2024-12-06 11:25:43 +01:00
Martin Povišer	d57d21e566	wrapcell: Optionally track unused outputs	2024-12-05 18:16:53 +01:00
Akash Levy	4356eae4c9	Yosys sync	2024-12-04 14:16:55 -08:00
Martin Povišer	59a96470df	Merge pull request #4773 from povik/wrapcell ... wrapcell: Add new command	2024-12-04 11:49:51 +01:00
Martin Povišer	14ee5ce800	Merge pull request #4787 from povik/booth-macc ... booth: Map simple `$macc` instances too	2024-12-04 11:49:34 +01:00
Emil J. Tywoniak	6edf9c86cb	libparse: add LibertyMergedCells, enable multiple -liberty args for dfflibmap and clockgate	2024-12-03 17:36:00 +01:00
Emil J	52336369fa	Merge pull request #4783 from YosysHQ/emil/blockrom-driver-conflict ... tests: fix blockrom.v driver conflict	2024-12-03 16:29:43 +01:00
Martin Povišer	109d97bb40	Merge pull request #4706 from povik/keep_hierarchy-adjustalgo ... Adjust `keep_hierarchy` behavior	2024-12-03 12:18:28 +01:00
Akash Levy	3914c21286	verific->import fix for new test case	2024-12-02 20:07:07 -05:00
Martin Povišer	f0704b6ede	Redo integer passing on top of bignum	2024-12-02 19:56:51 +01:00
Emil J. Tywoniak	c26966e3db	tests: fix blockrom.v driver conflict	2024-12-02 16:56:42 +01:00
Emil J. Tywoniak	fe64a714a9	techmap: add a Sklansky option for $lcu mapping	2024-12-02 11:34:58 +01:00
Akash Levy	6e88c689f2	Merge branch 'YosysHQ:main' into main	2024-12-01 12:32:07 -05:00
Martin Povišer	1ded817beb	booth: Map simple $macc instances too	2024-12-01 16:00:04 +01:00