Merge branch 'YosysHQ:main' into main

tests/various/tcl_apis.tcl

@@ -0,0 +1,63 @@
+yosys read_verilog tcl_apis.v
+
+if {[rtlil::get_attr -string -mod top foo] != "bar"} {
+	error "bad top module attribute"
+}
+
+if {[rtlil::get_attr -int -mod top val] != 4294967295} {
+	error "bad top module attribute 2"
+}
+
+if {[rtlil::get_attr -sint -mod top val] != -1} {
+	error "bad top module attribute 3"
+}
+
+if {[rtlil::get_attr -bool top w dont_touch] != 1} {
+	error "bad w wire attribute"
+}
+
+if {[rtlil::get_param -int top inst PARAM] != -3} {
+	error "bad parameter"
+}
+if {[rtlil::get_param -uint top inst PARAM] != 4294967293} {
+	error "bad parameter 2"
+}
+
+rtlil::set_attr -true -mod top marked
+yosys select -assert-any A:marked
+
+# write a 32-bit constant with most bits set
+rtlil::set_attr -mod -uint top f 4294967294
+# read it back as a signed integer
+if {[rtlil::get_attr -mod -sint top f] != -2} {
+	error "bad int roundtrip"
+}
+# read it back as an unsigned integer (no signedness flag)
+if {[rtlil::get_attr -mod -int top f] != 4294967294} {
+	error "bad int roundtrip 2"
+}
+# read it back as an unsigned integer
+if {[rtlil::get_attr -mod -uint top f] != 4294967294} {
+	error "bad int roundtrip 3"
+}
+
+# write a signed 32-bit constant
+rtlil::set_attr -mod -sint top f -3
+# read it back as a signed integer
+if {[rtlil::get_attr -mod -sint top f] != -3} {
+	error "bad int roundtrip 4"
+}
+# read it back as a signed integer (due to signedness flag)
+if {[rtlil::get_attr -mod -int top f] != -3} {
+	error "bad int roundtrip 5"
+}
+# read it back as an unsigned integer
+if {[rtlil::get_attr -mod -uint top f] != 4294967293} {
+	error "bad int roundtrip 6"
+}
+
+# write a constant larger than 32 bits
+rtlil::set_attr -mod -sint top prime 87178291199
+if {[rtlil::get_attr -mod -int top prime] != 87178291199} {
+	error "bad int roundtrip 7"
+}

tests/various/tcl_apis.v

@@ -0,0 +1,12 @@
+module m;
+parameter PARAM = 0;
+endmodule
+
+(* foo="bar" *)
+(* val=32'hffffffff *)
+module top;
+	(* dont_touch *)
+	wire w;
+
+	m #(.PARAM(-3)) inst();
+endmodule

tests/various/tcl_apis.ys

@@ -0,0 +1 @@
+tcl tcl_apis.tcl

tests/verific/blackbox_empty.ys

@@ -0,0 +1,17 @@
+verific -sv  <<EOF
+module TEST_CELL(input clk, input a, input b, output reg c);
+parameter PATH = "DEFAULT";
+endmodule
+EOF
+
+verific -sv <<EOF
+module top(input clk, input a, input b, output c, output d);
+	TEST_CELL  #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
+	TEST_CELL  #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
+endmodule
+EOF
+
+verific -import top
+hierarchy -top top
+stat
+select -assert-count 2 t:TEST_CELL

tests/verific/blackbox_ql.ys

@@ -0,0 +1,41 @@
+verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v 
+
+verific -sv <<EOF
+module top (
+    input  wire [19:0] a,
+    input  wire [17:0] b,
+    output wire [37:0] z,
+    input  wire       clk,
+    input  wire       reset,
+    input  wire       unsigned_a,
+    input  wire       unsigned_b,
+    input  wire       f_mode,
+    input  wire [2:0] output_select,
+    input  wire       register_inputs
+);
+	
+// module instantiation
+QL_DSP2_MULT_REGIN_REGOUT #(
+    .MODE_BITS(80'h1232324)
+) u1 (
+    .a (a),
+    .b (b),
+    .z (z),
+    .clk (clk),
+    .reset (reset),
+
+    .unsigned_a (unsigned_a),
+    .unsigned_b (unsigned_b),
+
+    .f_mode (f_mode),
+    .output_select (output_select),
+    .register_inputs (register_inputs)
+);
+endmodule
+
+EOF
+
+verific -import top
+hierarchy -top top
+synth_quicklogic -family qlf_k6n10f
+select -assert-count 1 t:QL_DSP2_MULT_REGIN_REGOUT a:MODE_BITS=80'h1232324