mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

Yosys sync

Browse source
This commit is contained in:
Akash Levy 2024-12-04 14:16:55 -08:00
commit 4356eae4c9
54 changed files with 1651 additions and 1040 deletions
Download patch file Download diff file Expand all files Collapse all files

8
tests/arch/common/blockrom.v
View file

@ -10,8 +10,11 @@ module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
reg [WORD:0] data_out_r;
reg [WORD:0] memory [0:DEPTH];
integer i,j = 64'hF4B1CA8127865242;
initial
integer i,j;
// Initialize in initial block as a workaround for
// https://github.com/YosysHQ/yosys/issues/4792
initial begin
j = 64'hF4B1CA8127865242;
for (i = 0; i <= DEPTH; i++) begin
// In case this ROM will be implemented in fabric: fill the memory with some data
// uncorrelated with the address, or Yosys might see through the ruse and e.g. not
@ -21,6 +24,7 @@ module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
j = j ^ (j << 25);
j = j ^ (j >> 27);
end
end
always @(posedge clk) begin
data_out_r <= memory[address_in];

17
tests/techmap/booth.ys
View file

@ -10,6 +10,19 @@ endmodule
EOF
booth
sat -verify -set a 0 -set b 0 -prove y 0
design -reset
test_cell -s 1694091355 -n 100 -script booth_map_script.ys_ $mul
design -reset
test_cell -s 1694091355 -n 100 -script booth_map_script.ys_ $mul
design -reset
read_verilog <<EOF
module top(a,b,y);
input wire [4:0] a;
input wire [5:0] b;
output wire [6:0] y;
assign y = a * b;
endmodule
EOF
synth -run :fine
# test compatibility with alumacc
equiv_opt -assert booth

43
tests/techmap/clockgate.ys
View file

@ -235,6 +235,49 @@ select -module dffe_11 -assert-count 0 t:\$_NOT_
#------------------------------------------------------------------------------
# test multiple liberty files to behave the same way
design -load before
clockgate -liberty clockgate_pos.lib -liberty clockgate_neg.lib
# rising edge ICGs
select -module dffe_00 -assert-count 0 t:\\pos_small
select -module dffe_01 -assert-count 0 t:\\pos_small
select -module dffe_10 -assert-count 1 t:\\pos_small
select -module dffe_11 -assert-count 1 t:\\pos_small
# falling edge ICGs
select -module dffe_00 -assert-count 1 t:\\neg_small
select -module dffe_01 -assert-count 1 t:\\neg_small
select -module dffe_10 -assert-count 0 t:\\neg_small
select -module dffe_11 -assert-count 0 t:\\neg_small
# and nothing else
select -module dffe_00 -assert-count 0 t:\\pos_big
select -module dffe_01 -assert-count 0 t:\\pos_big
select -module dffe_10 -assert-count 0 t:\\pos_big
select -module dffe_11 -assert-count 0 t:\\pos_big
select -module dffe_00 -assert-count 0 t:\\pos_small_tielo
select -module dffe_01 -assert-count 0 t:\\pos_small_tielo
select -module dffe_10 -assert-count 0 t:\\pos_small_tielo
select -module dffe_11 -assert-count 0 t:\\pos_small_tielo
select -module dffe_00 -assert-count 0 t:\\neg_big
select -module dffe_01 -assert-count 0 t:\\neg_big
select -module dffe_10 -assert-count 0 t:\\neg_big
select -module dffe_11 -assert-count 0 t:\\neg_big
select -module dffe_00 -assert-count 0 t:\\neg_small_tielo
select -module dffe_01 -assert-count 0 t:\\neg_small_tielo
select -module dffe_10 -assert-count 0 t:\\neg_small_tielo
select -module dffe_11 -assert-count 0 t:\\neg_small_tielo
# if necessary, EN is inverted, since the given ICG
# is assumed to have an active-high EN
select -module dffe_10 -assert-count 1 t:\$_NOT_
select -module dffe_11 -assert-count 0 t:\$_NOT_
#------------------------------------------------------------------------------
design -load before
clockgate -liberty clockgate.lib -dont_use pos_small -dont_use neg_small

55
tests/techmap/clockgate_neg.lib Normal file
View file

@ -0,0 +1,55 @@
library(test) {
/* Integrated clock gating cells */
cell (neg_big) {
area : 10;
clock_gating_integrated_cell : latch_negedge;
pin (GCLK) {
clock_gate_out_pin : true;
direction : output;
}
pin (CLK) {
clock_gate_clock_pin : true;
direction : input;
}
pin (CE) {
clock_gate_enable_pin : true;
direction : input;
}
}
cell (neg_small_tielo) {
area : 1;
clock_gating_integrated_cell : latch_negedge_precontrol;
pin (GCLK) {
clock_gate_out_pin : true;
direction : output;
}
pin (CLK) {
clock_gate_clock_pin : true;
direction : input;
}
pin (CE) {
clock_gate_enable_pin : true;
direction : input;
}
pin (SE) {
clock_gate_test_pin : true;
direction : input;
}
}
cell (neg_small) {
area : 1;
clock_gating_integrated_cell : latch_negedge;
pin (GCLK) {
clock_gate_out_pin : true;
direction : output;
}
pin (CLK) {
clock_gate_clock_pin : true;
direction : input;
}
pin (CE) {
clock_gate_enable_pin : true;
direction : input;
}
}
}

55
tests/techmap/clockgate_pos.lib Normal file
View file

@ -0,0 +1,55 @@
library(test) {
/* Integrated clock gating cells */
cell (pos_small_tielo) {
area : 1;
clock_gating_integrated_cell : latch_posedge_precontrol;
pin (GCLK) {
clock_gate_out_pin : true;
direction : output;
}
pin (CLK) {
clock_gate_clock_pin : true;
direction : input;
}
pin (CE) {
clock_gate_enable_pin : true;
direction : input;
}
pin (SE) {
clock_gate_test_pin : true;
direction : input;
}
}
cell (pos_big) {
area : 10;
clock_gating_integrated_cell : latch_posedge;
pin (GCLK) {
clock_gate_out_pin : true;
direction : output;
}
pin (CLK) {
clock_gate_clock_pin : true;
direction : input;
}
pin (CE) {
clock_gate_enable_pin : true;
direction : input;
}
}
cell (pos_small) {
area : 1;
clock_gating_integrated_cell : latch_posedge;
pin (GCLK) {
clock_gate_out_pin : true;
direction : output;
}
pin (CLK) {
clock_gate_clock_pin : true;
direction : input;
}
pin (CE) {
clock_gate_enable_pin : true;
direction : input;
}
}
}

10
tests/techmap/dfflibmap.ys
View file

@ -59,6 +59,16 @@ select -assert-count 1 t:dffn
select -assert-count 4 t:dffsr
select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
design -load orig
dfflibmap -prepare -liberty dfflibmap_dffn.lib -liberty dfflibmap_dffsr.lib
dfflibmap -map-only -liberty dfflibmap_dffn.lib -liberty dfflibmap_dffsr.lib
clean
select -assert-count 4 t:$_NOT_
select -assert-count 1 t:dffn
select -assert-count 4 t:dffsr
select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
design -load orig
dfflibmap -liberty dfflibmap.lib -dont_use *ffn
clean

23
tests/techmap/dfflibmap_dffn.lib Normal file
View file

@ -0,0 +1,23 @@
library(test) {
cell (dffn) {
area : 6;
ff("IQ", "IQN") {
next_state : "D";
clocked_on : "!CLK";
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
}

33
tests/techmap/dfflibmap_dffsr.lib Normal file
View file

@ -0,0 +1,33 @@
library(test) {
cell (dffsr) {
area : 6;
ff("IQ", "IQN") {
next_state : "D";
clocked_on : "CLK";
clear : "CLEAR";
preset : "PRESET";
clear_preset_var1 : L;
clear_preset_var2 : L;
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(CLEAR) {
direction : input;
}
pin(PRESET) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
}

15
tests/techmap/sklansky.tcl Normal file
View file

@ -0,0 +1,15 @@
yosys -import
read_verilog +/choices/sklansky.v
read_verilog -icells lcu_refined.v
design -save init
for {set i 1} {$i <= 16} {incr i} {
design -load init
chparam -set WIDTH $i
yosys proc
opt_clean
equiv_make lcu _80_lcu_sklansky equiv
equiv_simple equiv
equiv_status -assert equiv
}

53
tests/various/keep_hierarchy.ys Normal file
View file

@ -0,0 +1,53 @@
read_verilog <<EOF
(* blackbox *)
(* gate_cost_equivalent=150 *)
module macro;
endmodule
module branch1;
macro inst1();
macro inst2();
macro inst3();
endmodule
module branch2;
macro inst1();
macro inst2();
macro inst3();
macro inst4();
endmodule
// branch3_submod on its own doesn't meet the threshold
module branch3_submod();
wire [2:0] y;
wire [2:0] a;
wire [2:0] b;
assign y = a * b;
endmodule
// on the other hand four branch3_submods do
module branch3;
branch3_submod inst1();
branch3_submod inst2();
branch3_submod inst3();
branch3_submod inst4();
endmodule
// wrapper should have zero cost when branch3 is marked
// keep_hierarchy
module branch3_wrapper;
branch3 inst();
endmodule
module top;
branch1 inst1();
branch2 inst2();
branch3_wrapper wrapper();
endmodule
EOF
hierarchy -top top
keep_hierarchy -min_cost 500
select -assert-mod-count 2 A:keep_hierarchy
select -assert-any A:keep_hierarchy branch2 %i
select -assert-any A:keep_hierarchy branch3 %i

25
tests/various/wrapcell.ys Normal file
View file

@ -0,0 +1,25 @@
read_verilog <<EOF
module top(
input [1:0] a,
input [2:0] b,
output [2:0] y,
input [2:0] a2,
input [3:0] b2,
output [3:0] y2,
input [1:0] a3,
input [2:0] b3,
output [2:0] y3
);
assign y = a | (*keep*) b;
assign y2 = a2 | (*keep*) b2;
assign y3 = a3 | (*keep*) b3;
endmodule
EOF
wreduce
wrapcell -setattr foo -formatattr bar w{Y_WIDTH} -name OR_{A_WIDTH}_{B_WIDTH}_{Y_WIDTH}
select -assert-count 2 top/t:OR_2_3_3
select -assert-count 1 top/t:OR_3_4_4
select -assert-none top/t:OR_2_3_3 top/t:OR_3_4_4 %% top/t:* %D
select -assert-mod-count 2 OR_2_3_3 OR_3_4_4
select -assert-mod-count 2 A:bar=w3 A:bar=w4