1602 commits

Author	SHA1	Message	Date
Clifford Wolf	019b301541	Early wire/reg/parameter width calculation in ast/simplify	2013-11-24 19:40:23 +01:00
Clifford Wolf	0ef22c7609	Added support for signed parameters in ilang	2013-11-24 17:37:27 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	1de12e1efc	Improved handling of initialized registers	2013-11-23 16:26:59 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	a362fd81ae	Fixed O(n^2) performance bug in verilog preprocessor	2013-11-22 14:08:43 +01:00
Clifford Wolf	e4429c480e	Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)	2013-11-22 12:46:02 +01:00
Clifford Wolf	95c94a02fc	Fixed async proc detection in mem2reg	2013-11-21 21:26:56 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	08ceb3729e	Fixed ilang parser: memory width	2013-11-20 19:55:52 +01:00
Clifford Wolf	65ad556f3d	Another name resolution bugfix for generate blocks	2013-11-20 13:57:40 +01:00
Clifford Wolf	92035fb38e	Implemented indexed part selects	2013-11-20 13:05:27 +01:00
Clifford Wolf	c4c299eb5a	Do not allow memory bit select on the left side of an assignment	2013-11-20 12:18:46 +01:00
Clifford Wolf	0f04738f40	Added "synthesis" in (synopsys|synthesis) comment support	2013-11-20 11:44:09 +01:00
Clifford Wolf	ac2be2d892	Fixed name resolution of local tasks and functions in generate block	2013-11-20 11:05:58 +01:00
Clifford Wolf	19dba2561e	Implemented part/bit select on memory read	2013-11-20 10:51:32 +01:00
Clifford Wolf	e340532ce5	Added init= attribute for fpga-style reset values	2013-11-20 01:49:37 +01:00
Clifford Wolf	0dfdbd991a	Fixed parsing of module arguments when one type is used for many args	2013-11-19 20:35:31 +01:00
Clifford Wolf	4f2edcf2f9	Fixed two bugs in mem2reg functionality in AST frontend	2013-11-18 19:55:12 +01:00
Clifford Wolf	79910a5547	Added dumping of attributes in AST frontend	2013-11-18 19:54:36 +01:00
Clifford Wolf	2a25e3bca3	Fixed parsing of default cases when not last case	2013-11-18 16:10:50 +01:00
Clifford Wolf	de03184150	Fixed mem2reg for reg usage outside always block	2013-11-18 12:35:41 +01:00
Clifford Wolf	63060dcd2e	Fixed parsing of "parameter integer"	2013-11-13 15:30:23 +01:00
Clifford Wolf	e5b974fa2a	Cleanups and bugfixes in response to new internal cell checker	2013-11-11 00:39:45 +01:00
Clifford Wolf	378cc509cd	Call internal checker more often	2013-11-10 23:24:21 +01:00
Clifford Wolf	259cc1391e	More undef-propagation related fixes	2013-11-08 11:40:36 +01:00
Clifford Wolf	9f49d538e1	Fixed handling of different signedness in power operands	2013-11-08 11:06:11 +01:00
Clifford Wolf	4abc8e695a	Implemented const folding of ternary op with undef select	2013-11-08 04:44:09 +01:00
Clifford Wolf	fc6dc0d7b8	Fixed handling of power operator	2013-11-07 22:20:00 +01:00
Clifford Wolf	d7cb62ac96	Fixed more extend vs. extend_u0 issues	2013-11-07 19:20:20 +01:00
Clifford Wolf	02f4f89fdb	Disabled const folding of ternary op when select is undef	2013-11-07 18:18:16 +01:00
Clifford Wolf	947bd9b96b	Renamed extend_un0() to extend_u0() and use it in genrtlil	2013-11-07 18:17:10 +01:00
Clifford Wolf	ed4bcd52e5	Fixed sign handling in constants	2013-11-07 14:53:10 +01:00
Clifford Wolf	83a8b8b5ca	Fixed const folding in corner cases with parameters	2013-11-07 14:08:53 +01:00
Clifford Wolf	b52bf379b9	Fixed width detection for replicate operator	2013-11-07 12:43:04 +01:00
Clifford Wolf	536621a98b	Fixed at_zero evaluation of dynamic ranges	2013-11-07 11:25:19 +01:00
Clifford Wolf	f050c40519	Various fixes for correct parameter support	2013-11-07 10:02:11 +01:00
Clifford Wolf	160adccca2	Fixed the fix for propagation of width hints for $signed() and $unsigned()	2013-11-07 03:01:28 +01:00
Clifford Wolf	7fe13faefa	Fixed propagation of width hints for $signed() and $unsigned()	2013-11-06 22:41:21 +01:00
Clifford Wolf	baeca48a24	Additional fixes for undef propagation in concat and replicate ops	2013-11-06 21:16:54 +01:00
Clifford Wolf	6fcbc79b5c	Improved width extension with regard to undef propagation	2013-11-06 21:05:11 +01:00
Clifford Wolf	f2786df146	Another fix for early width and sign detection in ast simplifier	2013-11-04 21:29:36 +01:00
Clifford Wolf	d38c67f53d	Fixed const folding of ternary operator	2013-11-04 16:46:14 +01:00
Clifford Wolf	8d226da694	Use proper bit width ans sign extension for const folding	2013-11-04 15:37:09 +01:00
Clifford Wolf	1325514d33	Fixes for early width and sign detection in ast simplifier	2013-11-04 08:28:13 +01:00
Clifford Wolf	472117d532	further improved early width and sign detection in ast simplifier	2013-11-04 06:04:42 +01:00
Clifford Wolf	d2b083f5cb	Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT	2013-11-03 18:56:45 +01:00
Clifford Wolf	ada80545fa	Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)	2013-11-02 21:13:01 +01:00
Clifford Wolf	943329c1dc	Various ast changes for early expression width detection (prep for constfold fixes)	2013-11-02 13:00:17 +01:00