mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 01:55:33 +00:00
Code Activity

Cleanups and bugfixes in response to new internal cell checker

Browse source
This commit is contained in:
Clifford Wolf 2013-11-11 00:02:28 +01:00
parent 0fd3ebdb23
commit e5b974fa2a
5 changed files with 52 additions and 52 deletions
Download patch file Download diff file Expand all files Collapse all files

9
frontends/ast/genrtlil.cc
View file

@ -1199,7 +1199,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
addr_bits++;
cell->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx, 1);
cell->connections["\\ADDR"] = children[0]->genRTLIL();
cell->connections["\\ADDR"] = children[0]->genWidthRTLIL(addr_bits);
cell->connections["\\DATA"] = RTLIL::SigSpec(wire);
cell->parameters["\\MEMID"] = RTLIL::Const(str);
@ -1229,10 +1229,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
addr_bits++;
cell->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx, 1);
cell->connections["\\ADDR"] = children[0]->genRTLIL();
cell->connections["\\DATA"] = children[1]->genRTLIL();
cell->connections["\\ADDR"] = children[0]->genWidthRTLIL(addr_bits);
cell->connections["\\DATA"] = children[1]->genWidthRTLIL(current_module->memories[str]->width);
cell->connections["\\EN"] = children[2]->genRTLIL();
if (cell->connections["\\EN"].width > 1)
cell->connections["\\EN"] = uniop2rtlil(this, "$reduce_bool", 1, cell->connections["\\EN"], false);
cell->parameters["\\MEMID"] = RTLIL::Const(str);
cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);