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Code Activity
yosys/frontends
History
Clifford Wolf e340532ce5 Added init= attribute for fpga-style reset values
2013-11-20 01:49:37 +01:00
..
ast Fixed two bugs in mem2reg functionality in AST frontend 2013-11-18 19:55:12 +01:00
ilang Fixed parsing of value-less attributes in ilang 2013-10-23 18:38:31 +02:00
verilog Added init= attribute for fpga-style reset values 2013-11-20 01:49:37 +01:00