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Fixed more extend vs. extend_u0 issues

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This commit is contained in:
Clifford Wolf 2013-11-07 19:19:53 +01:00
parent 02f4f89fdb
commit d7cb62ac96
3 changed files with 20 additions and 11 deletions
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4
frontends/ast/genrtlil.cc
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@ -961,7 +961,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
return sig;
}
// just pass thru the signal. the parent will evaluate the is_signed property and inperpret the SigSpec accordingly
// just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly
case AST_TO_SIGNED:
case AST_TO_UNSIGNED: {
RTLIL::SigSpec sig = children[0]->genRTLIL();
@ -1346,7 +1346,7 @@ RTLIL::SigSpec AstNode::genWidthRTLIL(int width, RTLIL::SigSpec *subst_from, RT
genRTLIL_subst_to = backup_subst_to;
if (width >= 0)
widthExtend(this, sig, width, is_signed);
sig.extend_u0(width, is_signed);
return sig;
}

2
frontends/ast/simplify.cc
View file

@ -441,7 +441,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
int width = children[1]->range_left - children[1]->range_right + 1;
if (width != int(children[0]->bits.size())) {
RTLIL::SigSpec sig(children[0]->bits);
sig.extend(width, children[0]->is_signed);
sig.extend_u0(width, children[0]->is_signed);
delete children[0];
children[0] = mkconst_bits(sig.as_const().bits, children[0]->is_signed);
}