Akash Levy
6530a3d150
Merge branch 'YosysHQ:main' into main
2025-06-04 11:10:27 -07:00
Emil J
378add3723
Merge pull request #5163 from YosysHQ/emil/fix-single-bit-vector-leak
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simplify: fix single_bit_vector memory leak
2025-06-04 17:00:54 +02:00
George Rennie
0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout
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read_verilog/astsimplify: copy inout ports in and out of functions/tasks
2025-06-04 14:23:08 +01:00
George Rennie
ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix
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read_verilog: fix -1 constant used to correct post increment/decrement
2025-06-04 14:22:32 +01:00
Emil J. Tywoniak
c37b7b3bf4
simplify: fix single_bit_vector memory leak
2025-06-04 10:32:03 +02:00
Akash Levy
e3a6b920d4
Merge branch 'YosysHQ:main' into main
2025-06-02 18:47:14 +02:00
George Rennie
45e8ff476e
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 01:09:03 +01:00
KrystalDelusion
545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global
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SystemVerilog: Fix typedef struct in global space
2025-05-31 09:59:26 +12:00
George Rennie
70291f0e49
read_verilog: fix -1 constant used to correct post increment/decrement
2025-05-30 14:38:25 +01:00
Akash Levy
e50a5974f7
Get rid of SYNTHESIS redefinition warning
2025-05-28 08:33:56 +02:00
Akash Levy
3fc74be3e2
Merge branch 'YosysHQ:main' into main
2025-05-28 01:54:49 +02:00
KrystalDelusion
489a12d6c1
Merge pull request #5141 from garytwong/unique-if
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Accept (and ignore) SystemVerilog unique/priority if.
2025-05-27 09:45:50 +12:00
Krystine Sherwin
32ce23458f
read_verilog: Mark struct as custom type
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Being a custom type means that it will be resolved *before* (e.g.) a wire can use it as a type.
2025-05-26 12:19:33 +12:00
Akash Levy
3a23e772dd
Merge branch 'YosysHQ:main' into main
2025-05-24 12:11:52 -07:00
Emil J
4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width
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rtlil: enable single-bit vector wires
2025-05-23 15:55:45 +02:00
Gary Wong
9770ece187
Accept (and ignore) SystemVerilog unique/priority if.
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Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.
This affects only the grammar accepted; the behaviour of conditionals
is not changed. (But accepting this syntax will provide scope for
possible optimisations as future work.)
Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
2025-05-22 19:28:28 -06:00
Akash Levy
ccc2ba41f2
Merge branch 'YosysHQ:main' into main
2025-05-12 15:02:55 -07:00
Emil J. Tywoniak
e5171d6aa1
verific: support single_bit_vector
2025-05-12 13:23:29 +02:00
Emil J. Tywoniak
5e72464a15
rtlil: enable single-bit vector wires
2025-05-12 13:23:29 +02:00
Krystine Sherwin
fe0abb7026
simplify.cc: Fix mem leak
2025-05-10 17:10:47 +12:00
Akash Levy
3bcbfe4dde
verific -set_relaxed_file_libext_modes
2025-05-08 23:43:23 -07:00
Akash Levy
f3d24aea76
Add spaces in verific
2025-05-08 22:24:10 -07:00
Akash Levy
380850321d
Refactor verific -optimization and -no_split_complex_ports into verific pass
2025-05-08 15:59:47 -07:00
Akash Levy
7191be492c
Merge branch 'YosysHQ:main' into main
2025-05-05 15:36:40 -07:00
Krystine Sherwin
23cb007068
verilog_parser.y: Delete unused TOK_ID
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Fixes memory leak when parameter has no value.
2025-05-05 10:04:13 +12:00
Akash Levy
618cf9d372
Merge branch 'YosysHQ:main' into main
2025-04-28 13:57:29 -07:00
N. Engelhardt
8bdbf797d0
Merge pull request #5017 from YosysHQ/micko/ram_blasting
2025-04-28 13:33:48 +00:00
Akash Levy
94bc6937d3
Merge branch 'YosysHQ:main' into main
2025-04-27 15:24:30 -07:00
Emil J. Tywoniak
bdc2597f79
simplify: fix struct wiretype attr memory leak
2025-04-25 01:00:08 +02:00
Miodrag Milanovic
22e6ce4282
verific: bit blast RAM if using mem2reg attribute
2025-04-14 15:24:11 +02:00
Akash Levy
3e24a3e248
Bump yosys to latest
2025-04-08 18:05:28 -07:00
Miodrag Milanovic
406ee4c8d3
read_verilog_file_list: change short help message to start with lower case
2025-04-08 13:20:16 +02:00
Akash Levy
06c614a010
Merge branch 'YosysHQ:main' into main
2025-04-07 07:28:06 -07:00
Akash Levy
61715c2c28
Fix memory too large issue
2025-04-04 03:22:22 -07:00
Akash Levy
f218b5ba58
Revert "Represent memory size with size_t"
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This reverts commit bb5f8415af
2025-04-04 03:20:07 -07:00
Akash Levy
bb5f8415af
Represent memory size with size_t
2025-04-04 02:04:34 -07:00
Jannis Harder
0f13b55173
Liberty file caching with new libcache command
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This adds optional in-memory caching of parsed liberty files to speed up
flows that repeatedly parse the same liberty files. To avoid increasing
the memory overhead by default, the caching is disabled by default. The
caching can be controlled globally or on a per path basis using the new
`libcache` command, which also allows purging cached data.
2025-04-03 13:39:35 +02:00
Akash Levy
4bd08ac362
Merge branch 'YosysHQ:main' into main
2025-04-01 22:10:43 -07:00
Miodrag Milanovic
72f2185a94
verific: fix restoring msg state after blackbox import
2025-04-01 17:35:59 +02:00
Akash Levy
d2028feefe
Set Verific flags via -cfg instead of in Yosys
2025-03-25 22:41:06 -07:00
Akash Levy
95f489beec
Merge nice gzip refactor
2025-03-20 16:47:12 -07:00
Emil J. Tywoniak
813f909460
gzip: istream
2025-03-19 13:43:44 +01:00
Emil J. Tywoniak
4f3fdc8457
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
Alain Dargelas
3021dab37d
memory limit fix and increased limit
2025-03-17 09:07:33 -07:00
Akash Levy
bc3ca6210c
Add back operator optimization for Verific frontend
2025-03-17 04:06:28 -07:00
Akash Levy
1c0d4a43b3
Merge branch 'YosysHQ:main' into main
2025-03-14 18:07:55 -07:00
Alain Dargelas
88211310fa
code review
2025-03-12 16:32:42 -07:00
Alain Dargelas
dcce15207e
Memory size check
2025-03-12 16:21:18 -07:00
Jason Xu
a5f34d04f8
Address comments
2025-03-11 18:50:44 -04:00
Jason Xu
98eefc5d1a
Add file list support to read pass
2025-03-07 20:44:21 -05:00
