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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-05-05 15:36:40 -07:00 • committed by GitHub
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frontends/verilog/verilog_parser.y
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@ -2249,7 +2249,8 @@ cell_parameter:
node->children.push_back($1);
} |
'.' TOK_ID '(' ')' {
// just ignore empty parameters
// delete unused TOK_ID
delete $2;
} |
'.' TOK_ID '(' expr ')' {
AstNode *node = new AstNode(AST_PARASET);