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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-06-04 11:10:27 -07:00 • committed by GitHub
commit 6530a3d150
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4 changed files with 217 additions and 8 deletions
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22
frontends/ast/simplify.cc
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@ -2087,7 +2087,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
std::swap(range_left, range_right);
range_swapped = force_upto;
}
if (range_left == range_right)
if (range_left == range_right && !attributes.count(ID::single_bit_vector))
set_attribute(ID::single_bit_vector, mkconst_int(1, false));
}
} else {
@ -4100,16 +4100,24 @@ skip_dynamic_range_lvalue_expansion:;
delete arg;
continue;
}
AstNode *wire_id = new AstNode(AST_IDENTIFIER);
wire_id->str = wire->str;
AstNode *assign = child->is_input ?
new AstNode(AST_ASSIGN_EQ, wire_id, arg) :
new AstNode(AST_ASSIGN_EQ, arg, wire_id);
assign->children[0]->was_checked = true;
if (child->is_input)
if (child->is_input) {
AstNode *assign = new AstNode(AST_ASSIGN_EQ, wire_id->clone(), arg->clone());
assign->children[0]->was_checked = true;
new_stmts.push_back(assign);
else
}
if (child->is_output) {
AstNode *assign = new AstNode(AST_ASSIGN_EQ, arg->clone(), wire_id->clone());
assign->children[0]->was_checked = true;
output_assignments.push_back(assign);
}
delete arg;
delete wire_id;
}
}

3
frontends/verilog/verilog_parser.y
View file

@ -336,7 +336,8 @@ static AstNode *addIncOrDecExpr(AstNode *lhs, dict<IdString, AstNode*> *attr, AS
log_assert(stmt->type == AST_ASSIGN_EQ);
AstNode *expr = stmt->children[0]->clone();
if (undo) {
AstNode *minus_one = AstNode::mkconst_int(-1, true, 1);
AstNode *one = AstNode::mkconst_int(1, false, 1);
AstNode *minus_one = new AstNode(AST_NEG, one);
expr = new AstNode(op, expr, minus_one);
}
SET_AST_NODE_LOC(expr, begin, end);