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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-05-24 12:11:52 -07:00 • committed by GitHub
commit 3a23e772dd
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12 changed files with 87 additions and 9 deletions
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1
frontends/ast/genrtlil.cc
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@ -1446,6 +1446,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_input = is_input;
wire->port_output = is_output;
wire->upto = range_swapped;
wire->is_signed = is_signed;
for (auto &attr : attributes) {

6
frontends/ast/simplify.cc
View file

@ -2086,6 +2086,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
std::swap(range_left, range_right);
range_swapped = force_upto;
}
if (range_left == range_right)
set_attribute(ID::single_bit_vector, mkconst_int(1, false));
}
} else {
if (!range_valid)
@ -2094,6 +2096,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
range_swapped = false;
range_left = 0;
range_right = 0;
if (attributes.count(ID::single_bit_vector)) {
delete attributes[ID::single_bit_vector];
attributes.erase(ID::single_bit_vector);
}
}
}

4
frontends/verific/verific.cc
View file

@ -1629,6 +1629,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
wire->upto = portbus->IsUp();
import_attributes(wire->attributes, portbus, nl, portbus->Size());
if (portbus->Size() == 1)
wire->set_bool_attribute(ID::single_bit_vector);
SetIter si ;
Port *port ;
FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
@ -1826,6 +1828,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
break;
}
import_attributes(wire->attributes, netbus, nl, netbus->Size());
if (netbus->Size() == 1)
wire->set_bool_attribute(ID::single_bit_vector);
RTLIL::Const initval = Const(State::Sx, GetSize(wire));
bool initval_valid = false;