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Refactor verific -optimization and -no_split_complex_ports into verific pass

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This commit is contained in:
Akash Levy 2025-05-08 15:59:47 -07:00
parent e8fcbd7588
commit 380850321d
3 changed files with 24 additions and 23 deletions
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22
frontends/verific/verific.cc
View file

@ -120,6 +120,8 @@ int verific_verbose;
bool verific_import_pending;
string verific_error_msg;
int verific_sva_fsm_limit;
bool verific_opt; // SILIMATE: enable Verific optimizations
bool verific_no_split_complex_ports; // SILIMATE: disable splitting of complex ports
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
vector<string> verific_incdirs, verific_libdirs, verific_libexts;
@ -3078,7 +3080,7 @@ void verific_cleanup()
verific_import_pending = false;
}
std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top, bool opt, bool no_split_complex_port)
std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
{
verific_sva_fsm_limit = 16;
@ -3120,7 +3122,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str());
if (!no_split_complex_port)
if (!verific_no_split_complex_ports)
for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */);
@ -3132,8 +3134,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
auto it = nl_todo.begin();
Netlist *nl = it->second;
// SILIMATE: use Verific optimization
if (opt) {
// SILIMATE: use Verific optimizations
if (verific_opt) {
log(" Optimizing netlist for %s.\n", it->first.c_str());
log(" Inferring clock enable muxes for %s.\n", it->first.c_str());
@ -3606,6 +3608,10 @@ struct VerificPass : public Pass {
verific_verbose = 0;
verific_sva_fsm_limit = 16;
// SILIMATE: added flags
verific_opt = false;
verific_no_split_complex_ports = false;
const char *release_str = Message::ReleaseString();
time_t release_time = Message::ReleaseDate();
char *release_tmstr = ctime(&release_time);
@ -3753,6 +3759,14 @@ struct VerificPass : public Pass {
}
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && args[argidx] == "-optimization") {
verific_opt = true;
goto check_error;
}
if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") {
verific_no_split_complex_ports = true;
goto check_error;
}
if (GetSize(args) > argidx && args[argidx] == "-set_ignore_translate_off") {
veri_file::SetIgnoreTranslateOff(1);
goto check_error;

5
frontends/verific/verific.h
View file

@ -26,8 +26,11 @@ YOSYS_NAMESPACE_BEGIN
extern int verific_verbose;
extern bool verific_opt; // SILIMATE: enable Verific optimizations
extern bool verific_no_split_complex_ports; // SILIMATE: disable splitting of complex ports
extern bool verific_import_pending;
extern std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string(), bool opt = true, bool no_split_complex_ports = true);
extern std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string());
extern pool<int> verific_sva_prims;

20
passes/hierarchy/hierarchy.cc
View file

@ -794,12 +794,6 @@ struct HierarchyPass : public Pass {
log(" -auto-top\n");
log(" automatically determine the top of the design hierarchy and mark it.\n");
log("\n");
log(" -opt\n");
log(" optimize all modules in design hierarchy.\n");
log("\n");
log(" -no_split_complex_ports\n");
log(" Complex ports (structs or arrays) are not split and remain packed as a single port.\n");
log("\n");
log(" -chparam name value \n");
log(" elaborate the top module using this parameter value. Modules on which\n");
log(" this parameter does not exist may cause a warning message to be output.\n");
@ -827,8 +821,6 @@ struct HierarchyPass : public Pass {
{
log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");
bool flag_opt = false;
bool flag_no_split_complex_ports = false;
bool flag_check = false;
bool flag_simcheck = false;
bool flag_smtcheck = false;
@ -940,14 +932,6 @@ struct HierarchyPass : public Pass {
auto_top_mode = true;
continue;
}
if (args[argidx] == "-opt") {
flag_opt = true;
continue;
}
if (args[argidx] == "-no_split_complex_ports") {
flag_no_split_complex_ports = true;
continue;
}
if (args[argidx] == "-chparam" && argidx+2 < args.size()) {
const std::string &key = args[++argidx];
const std::string &value = args[++argidx];
@ -1002,7 +986,7 @@ struct HierarchyPass : public Pass {
if (top_mod == nullptr && !load_top_mod.empty()) {
#ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending) {
load_top_mod = verific_import(design, parameters, load_top_mod, flag_opt, flag_no_split_complex_ports);
load_top_mod = verific_import(design, parameters, load_top_mod);
top_mod = design->module(RTLIL::escape_id(load_top_mod));
}
#endif
@ -1011,7 +995,7 @@ struct HierarchyPass : public Pass {
} else {
#ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending)
verific_import(design, parameters, std::string(), flag_opt, flag_no_split_complex_ports);
verific_import(design, parameters, std::string());
#endif
}