Lofty
64c2491c24
analogdevices: user retargeting
2025-10-14 14:13:15 +01:00
Lofty
dcc2c3e86f
analogdevices: more housekeeping
2025-10-14 14:13:15 +01:00
Lofty
1b0eee8c24
analogdevices: remove some extra cells!
2025-10-14 14:13:15 +01:00
Lofty
40dbea0235
test suite
2025-10-14 14:13:15 +01:00
Lofty
58701cb380
synth_analogdevices: remove scopeinfo cells
2025-10-14 14:13:15 +01:00
Lofty
4ca199c9a2
Create synth_analogdevices
2025-10-14 14:13:15 +01:00
YRabbit
02e40e8118
Gowin. Reduce the range of flip-flop types.
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UG303-1.0E_Arora Ⅴ Configurable Function Unit (CFU) User Guide.pdf
specifies that the only flip-flop types supported in GW5 are DFFSE,
DFFRE, DFFPE, and DFFCE.
However, the bit streams generated by the vendor IDE also contain DFF
flip-flops, which are probably the result of optimisation, so we leave
them in the list of permitted items, but add a flag that will allow the
generation of completely correct output files, acceptable for further P&
R using vendor tools (they will not allow the use of flip-flops other
than the four specified in the netlist).
In the GW5 SemiDual Port BSRAM series, the primitive does not have
RESETA and RESETB ports—they are replaced by the RESET port, so we
separate the files for BSRAM generation, especially since in the future
we may have to take into account other, as yet unexplored, differences
in BSRAM.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-11 21:12:35 +10:00
Miodrag Milanović
869910055f
Merge pull request #3908 from YosysHQ/ecp5_2_lattice
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synth_ecp5 and synth_nexus to synth_lattice
2025-10-08 13:07:33 +02:00
Ethan Sifferman
d5beb65d30
added SIMLIB_VERILATOR_COMPAT
2025-10-01 10:19:25 -07:00
Miodrag Milanovic
714603bf69
synth_nexus to synth_lattice
2025-09-26 19:45:03 +01:00
Miodrag Milanovic
58f9531bfb
enable ABC9 by default except for XO2/3/3D
2025-09-25 15:44:05 +01:00
Miodrag Milanović
4b9e4bfae9
Update techlibs/lattice/synth_lattice.cc
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Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-09-25 15:44:05 +01:00
Miodrag Milanovic
faf82a5ff5
Add help message for synth_ecp5
2025-09-25 15:44:05 +01:00
Miodrag Milanovic
47a2215fe0
Update filenames and location for test script
2025-09-25 15:44:05 +01:00
Miodrag Milanovic
4a7f94f1c1
Enable synth_ecp5 wrapper and copy sim files for backwards compatibility
2025-09-25 15:44:05 +01:00
Miodrag Milanovic
e7ac237499
Delete synth_ecp5
2025-09-25 15:44:03 +01:00
Miodrag Milanovic
cfe53b7395
Move diamond tests
2025-09-25 15:38:57 +01:00
Miodrag Milanovic
b94b39cd40
Special DP16KD model is required
2025-09-25 15:38:55 +01:00
Ethan Sifferman
0eb93c80e6
added ifndef SIMLIB_NOCONNECT
2025-09-24 20:50:47 -07:00
Emil J. Tywoniak
d30f7847d8
techmap: map $alu to $fa instead of relying on extract_fa
2025-09-23 17:05:12 +02:00
Robert O'Callahan
1e5f920dbd
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
Emil J
a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort
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write_rtlil: don't sort
2025-09-22 11:14:39 +02:00
YRabbit
d60dc93e92
Gowin. Renaming inputs of the DCS primitive.
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The dynamic clock selection (DCS) primitive has undergone changes with
the release of the GW5A series—the CLK0,1,2,3 inputs are now
CLKIN0,1,2,3, but only for GW5A series chips.
There are no functional changes, only renaming.
Here we are transferring the description of the DCS primitive from
general to specialized files for each chip series.
We have also fixed a bug in the generation script that caused the loss
of primitive parameters. Fortunately, this only affected the
analog-to-digital converter, which has not yet been implemented.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-09-20 16:22:23 +01:00
Jannis Harder
1251e92e3a
Add $input_port and $connect cell types
2025-09-17 13:56:46 +02:00
Robert O'Callahan
a7c46f7b4a
Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()
2025-09-16 23:02:16 +00:00
Robert O'Callahan
5ac6858f26
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
Emil J. Tywoniak
73747f6928
read_verilog: add -relativeshare for synthesis reproducibility testing
2025-09-16 15:47:35 +02:00
Robert O'Callahan
1a367b907c
Use fast path for 32-bit Const integer constructor in more places
2025-09-16 03:17:24 +00:00
Robert O'Callahan
09b493cfcd
Update techlibs to avoid bits()
2025-09-16 03:17:23 +00:00
Robert O'Callahan
e0ae7b7af4
Remove .c_str() calls from log()/log_error()
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There are some leftovers, but this is an easy regex-based approach that removes most of them.
2025-09-11 20:59:37 +00:00
Robert O'Callahan
c7df6954b9
Remove .c_str() from stringf parameters
2025-09-01 23:34:42 +00:00
N. Engelhardt
15d24bf2e6
synth_quicklogic: add -noflatten option
2025-08-25 17:25:58 +02:00
Miodrag Milanović
c7e6275d0d
Merge pull request #5045 from danderson/push-nwpulrqymkqp
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techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes
2025-08-25 15:28:34 +02:00
Robert O'Callahan
8b75c06141
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
Martin Povišer
9ab1946799
Merge pull request #5209 from povik/hieropt
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Start `opt_hier` to enable hierarchical optimization
2025-07-17 14:12:18 +02:00
Martin Povišer
415b7d3f65
Drop experimental label off synth -hieropt
2025-07-17 12:02:44 +02:00
Martin Povišer
22a44e4333
Start opt_hier
2025-07-05 16:45:52 +02:00
YRabbit
85e7c68fc6
Gowin. BUGFIX. Fix multi-line descriptions.
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If let's say the enumeration of inputs took several lines, then all
after the first one were ignored. Since the first line ended with a
comma, an error was generated when trying to use the resulting file.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-07-02 12:39:18 +10:00
KrystalDelusion
5268565410
Merge pull request #5108 from marzoul/adrien-uram
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Create a single-port URAM mapping to support memories 2048 x 144b
2025-05-13 09:54:36 +12:00
Adrien Prost-Boucle
6bf7587338
URAM mapping : Add test for 2048 x 144b
2025-05-10 14:53:56 +02:00
Adrien Prost-Boucle
c7de531231
URAM mapping : Fix port indexes according to Yosys warnings
2025-05-09 15:09:11 +02:00
Adrien Prost-Boucle
c4a49f0c55
Create a single-port URAM mapping to support memories 2048 x 144b
2025-05-09 14:16:03 +02:00
Patrick Urban
6d575918fc
gatemate: Set unused BRAM inputs to 'bx
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This will reduce the number of CPEs to generate fixed values at the block RAM inputs, if it is not used.
2025-04-28 14:42:16 +02:00
KrystalDelusion
2d6255175e
Merge pull request #5057 from secworks/blocking_assignment_greenpak4_cells_sim_digital
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Change to use blocking assignments in non-clocked processes.
2025-04-26 11:15:10 +12:00
KrystalDelusion
6564810ae3
Merge pull request #4992 from Anhijkt/fix-ice40dsp-unsigned
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ice40_dsp: fix const handling
2025-04-26 11:15:02 +12:00
Miodrag Milanović
febc07e6fb
Merge pull request #5039 from YosysHQ/gatemate_bram
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gatemate: WRITE_THROUGH mode change
2025-04-25 09:53:43 +02:00
Emil J
f8c027b70e
Merge pull request #5056 from secworks/blocking_assignment_gatemate_cells_sim
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Change to blocking assignments in non-clocked process.
2025-04-23 23:13:54 +02:00
Joachim Strömbergson
2fcb61adb5
Change to use blocking assignments in non-clocked processes.
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2025-04-23 17:21:32 +02:00
Joachim Strömbergson
90f50722ab
Change to blocking assignments in non-clocked process.
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2025-04-23 17:13:37 +02:00
Joachim Strömbergson
e4d6781088
Changing non clocked alway assignment to blocking.
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2025-04-23 16:59:53 +02:00
