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https://github.com/YosysHQ/yosys
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Remove .c_str() calls from log()/log_error()
There are some leftovers, but this is an easy regex-based approach that removes most of them.
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parent
c2291c10a6
commit
e0ae7b7af4
140 changed files with 623 additions and 623 deletions
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@ -298,7 +298,7 @@ struct Coolrunner2FixupPass : public Pass {
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if ((!sig_fed_by_xor[input] && !sig_fed_by_io[input]) ||
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(sig_fed_by_io[input] && ibuf_out_to_packed_reg_cell[input] != cell))
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{
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log("Buffering input to \"%s\"\n", cell->name.c_str());
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log("Buffering input to \"%s\"\n", cell->name);
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auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str());
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@ -320,7 +320,7 @@ struct Coolrunner2FixupPass : public Pass {
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if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock])
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{
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log("Buffering clock to \"%s\"\n", cell->name.c_str());
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log("Buffering clock to \"%s\"\n", cell->name);
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auto pterm_to_ff_wire = makeptermbuffer(module, clock);
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@ -338,7 +338,7 @@ struct Coolrunner2FixupPass : public Pass {
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{
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if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set])
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{
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log("Buffering set to \"%s\"\n", cell->name.c_str());
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log("Buffering set to \"%s\"\n", cell->name);
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auto pterm_to_ff_wire = makeptermbuffer(module, set);
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@ -352,7 +352,7 @@ struct Coolrunner2FixupPass : public Pass {
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{
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if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset])
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{
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log("Buffering reset to \"%s\"\n", cell->name.c_str());
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log("Buffering reset to \"%s\"\n", cell->name);
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auto pterm_to_ff_wire = makeptermbuffer(module, reset);
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@ -369,7 +369,7 @@ struct Coolrunner2FixupPass : public Pass {
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ce = sigmap(cell->getPort(ID(CE))[0]);
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if (!sig_fed_by_pterm[ce])
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{
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log("Buffering clock enable to \"%s\"\n", cell->name.c_str());
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log("Buffering clock enable to \"%s\"\n", cell->name);
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auto pterm_to_ff_wire = makeptermbuffer(module, ce);
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@ -389,7 +389,7 @@ struct Coolrunner2FixupPass : public Pass {
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if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) ||
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packed_reg_out[input])
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{
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log("Buffering input to \"%s\"\n", cell->name.c_str());
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log("Buffering input to \"%s\"\n", cell->name);
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auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str());
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@ -404,7 +404,7 @@ struct Coolrunner2FixupPass : public Pass {
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oe = sigmap(cell->getPort(ID::E)[0]);
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if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe])
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{
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log("Buffering output enable to \"%s\"\n", cell->name.c_str());
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log("Buffering output enable to \"%s\"\n", cell->name);
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auto pterm_to_oe_wire = makeptermbuffer(module, oe);
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@ -46,12 +46,12 @@ static void run_ice40_braminit(Module *module)
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continue;
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/* Open file */
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log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file.c_str());
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log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file);
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std::ifstream f;
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f.open(init_file.c_str());
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if (f.fail()) {
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log("Can not open file `%s`.\n", init_file.c_str());
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log("Can not open file `%s`.\n", init_file);
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continue;
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}
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@ -294,7 +294,7 @@ struct MicrochipDffOptPass : public Pass {
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ports += " + S";
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if (worthy_post_ce)
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ports += " + CE";
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log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire),
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log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire),
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GetSize(lut_d.second), GetSize(final_lut.second));
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// Okay, we're doing it. Unmap ports.
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@ -305,7 +305,7 @@ unmap:
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if (worthy_post_r) ports += " + R";
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if (worthy_post_s) ports += " + S";
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if (worthy_post_ce) ports += " + CE";
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log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
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log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
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// Okay, we're doing it. Unmap ports.
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if (worthy_post_r) {
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