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Remove .c_str() from stringf parameters

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This commit is contained in:
Robert O'Callahan 2025-08-19 22:45:26 +00:00
parent c41ba912d8
commit c7df6954b9
90 changed files with 773 additions and 773 deletions
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2
techlibs/achronix/synth_achronix.cc
View file

@ -123,7 +123,7 @@ struct SynthAchronixPass : public ScriptPass {
if (check_label("begin"))
{
run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))

6
techlibs/anlogic/synth_anlogic.cc
View file

@ -150,7 +150,7 @@ struct SynthAnlogicPass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
@ -233,13 +233,13 @@ struct SynthAnlogicPass : public ScriptPass
if (check_label("edif"))
{
if (!edif_file.empty() || help_mode)
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file));
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthAnlogicPass;

2
techlibs/common/prep.cc
View file

@ -177,7 +177,7 @@ struct PrepPass : public ScriptPass
else
run("hierarchy -check");
} else
run(stringf("hierarchy -check -top %s", top_module.c_str()));
run(stringf("hierarchy -check -top %s", top_module));
}
}

6
techlibs/common/synth.cc
View file

@ -249,7 +249,7 @@ struct SynthPass : public ScriptPass {
else
run("hierarchy -check");
} else
run(stringf("hierarchy -check -top %s", top_module.c_str()));
run(stringf("hierarchy -check -top %s", top_module));
}
}
@ -294,7 +294,7 @@ struct SynthPass : public ScriptPass {
if (!techmap_maps.empty())
techmap_opts += " -map +/techmap.v";
for (auto fn : techmap_maps)
techmap_opts += stringf(" -map %s", fn.c_str());
techmap_opts += stringf(" -map %s", fn);
run("techmap" + techmap_opts);
}
if (help_mode) {
@ -316,7 +316,7 @@ struct SynthPass : public ScriptPass {
run(abc + " -fast -lut k", "(unless -noabc, if -lut)");
} else {
if (lut)
run(stringf("%s -fast -lut %d", abc.c_str(), lut));
run(stringf("%s -fast -lut %d", abc, lut));
else
run(abc + " -fast");
}

4
techlibs/coolrunner2/synth_coolrunner2.cc
View file

@ -126,7 +126,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib +/coolrunner2/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
@ -198,7 +198,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthCoolrunner2Pass;

16
techlibs/easic/synth_easic.cc
View file

@ -129,14 +129,14 @@ struct SynthEasicPass : public ScriptPass
void script() override
{
string phys_clk_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_phys_clk_0v893ff125c.lib", etools_path.c_str());
string logic_lut_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_logic_lut_0v893ff125c.lib", etools_path.c_str());
string phys_clk_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_phys_clk_0v893ff125c.lib", etools_path);
string logic_lut_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_logic_lut_0v893ff125c.lib", etools_path);
if (check_label("begin"))
{
run(stringf("read_liberty -lib %s", help_mode ? "<etools_phys_clk_lib>" : phys_clk_lib.c_str()));
run(stringf("read_liberty -lib %s", help_mode ? "<etools_logic_lut_lib>" : logic_lut_lib.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("read_liberty -lib %s", help_mode ? "<etools_phys_clk_lib>" : phys_clk_lib));
run(stringf("read_liberty -lib %s", help_mode ? "<etools_logic_lut_lib>" : logic_lut_lib));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
@ -165,8 +165,8 @@ struct SynthEasicPass : public ScriptPass
if (check_label("map"))
{
run(stringf("dfflibmap -liberty %s", help_mode ? "<etools_phys_clk_lib>" : phys_clk_lib.c_str()));
run(stringf("abc -liberty %s", help_mode ? "<etools_logic_lut_lib>" : logic_lut_lib.c_str()));
run(stringf("dfflibmap -liberty %s", help_mode ? "<etools_phys_clk_lib>" : phys_clk_lib));
run(stringf("abc -liberty %s", help_mode ? "<etools_logic_lut_lib>" : logic_lut_lib));
run("opt_clean");
}
@ -181,7 +181,7 @@ struct SynthEasicPass : public ScriptPass
if (check_label("vlog"))
{
if (!vlog_file.empty() || help_mode)
run(stringf("write_verilog -noexpr -attr2comment %s", help_mode ? "<file-name>" : vlog_file.c_str()));
run(stringf("write_verilog -noexpr -attr2comment %s", help_mode ? "<file-name>" : vlog_file));
}
}
} SynthEasicPass;

10
techlibs/ecp5/synth_ecp5.cc
View file

@ -272,7 +272,7 @@ struct SynthEcp5Pass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("coarse"))
@ -383,9 +383,9 @@ struct SynthEcp5Pass : public ScriptPass
abc9_opts += " -maxlut 4";
std::string k = "synth_ecp5.abc9.W";
if (active_design && active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k));
else
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k));
if (nowidelut)
abc9_opts += " -maxlut 4";
if (dff)
@ -443,13 +443,13 @@ struct SynthEcp5Pass : public ScriptPass
if (check_label("edif"))
{
if (!edif_file.empty() || help_mode)
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file));
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthEcp5Pass;

6
techlibs/efinix/synth_efinix.cc
View file

@ -142,7 +142,7 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib +/efinix/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
@ -225,13 +225,13 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("edif"))
{
if (!edif_file.empty() || help_mode)
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file));
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthEfinixPass;

6
techlibs/fabulous/synth_fabulous.cc
View file

@ -278,7 +278,7 @@ struct SynthPass : public ScriptPass
else
run("hierarchy -check");
} else
run(stringf("hierarchy -check -top %s", top_module.c_str()));
run(stringf("hierarchy -check -top %s", top_module));
run("proc");
}
@ -365,7 +365,7 @@ struct SynthPass : public ScriptPass
} else if (!extra_map.empty()) {
std::string map_str = "techmap";
for (auto map : extra_map)
map_str += stringf(" -map %s", map.c_str());
map_str += stringf(" -map %s", map);
run(map_str);
}
run("clean");
@ -399,7 +399,7 @@ struct SynthPass : public ScriptPass
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthPass;

6
techlibs/gatemate/synth_gatemate.cc
View file

@ -203,7 +203,7 @@ struct SynthGateMatePass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("prepare"))
@ -351,14 +351,14 @@ struct SynthGateMatePass : public ScriptPass
{
run("opt_clean -purge");
if (!vlog_file.empty() || help_mode) {
run(stringf("write_verilog -noattr %s", help_mode ? "<file-name>" : vlog_file.c_str()));
run(stringf("write_verilog -noattr %s", help_mode ? "<file-name>" : vlog_file));
}
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode) {
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
}

4
techlibs/gowin/synth_gowin.cc
View file

@ -219,8 +219,8 @@ struct SynthGowinPass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -specify -lib +/gowin/cells_sim.v");
run(stringf("read_verilog -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "<family>" : family.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("read_verilog -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "<family>" : family));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))

4
techlibs/greenpak4/synth_greenpak4.cc
View file

@ -138,7 +138,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib +/greenpak4/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
@ -202,7 +202,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthGreenPAK4Pass;

4
techlibs/ice40/ice40_wrapcarry.cc
View file

@ -59,9 +59,9 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
cell->setParam(ID::LUT, st.lut->getParam(ID(LUT_INIT)));
for (const auto &a : st.carry->attributes)
cell->attributes[stringf("\\SB_CARRY.%s", a.first.c_str())] = a.second;
cell->attributes[stringf("\\SB_CARRY.%s", a.first)] = a.second;
for (const auto &a : st.lut->attributes)
cell->attributes[stringf("\\SB_LUT4.%s", a.first.c_str())] = a.second;
cell->attributes[stringf("\\SB_LUT4.%s", a.first)] = a.second;
cell->attributes[ID(SB_LUT4.name)] = Const(st.lut->name.str());
if (st.carry->get_bool_attribute(ID::keep) || st.lut->get_bool_attribute(ID::keep))
cell->attributes[ID::keep] = true;

12
techlibs/ice40/synth_ice40.cc
View file

@ -302,7 +302,7 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
run("proc");
}
@ -419,10 +419,10 @@ struct SynthIce40Pass : public ScriptPass
std::string abc9_opts;
std::string k = "synth_ice40.abc9.W";
if (active_design && active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k));
else {
k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str());
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
k = stringf("synth_ice40.abc9.%s.W", device_opt);
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k));
}
if (dff)
abc9_opts += " -dff";
@ -475,13 +475,13 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("edif"))
{
if (!edif_file.empty() || help_mode)
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file));
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthIce40Pass;

10
techlibs/intel/synth_intel.cc
View file

@ -188,12 +188,12 @@ struct SynthIntelPass : public ScriptPass {
{
if (check_label("begin")) {
if (check_label("family"))
run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt));
// Misc and common cells
run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("coarse")) {
@ -225,7 +225,7 @@ struct SynthIntelPass : public ScriptPass {
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL9X9");
run("chtype -set $mul t:$__soft_mul");
run("alumacc");
run(stringf("techmap -map +/intel/%s/dsp_map.v", family_opt.c_str()));
run(stringf("techmap -map +/intel/%s/dsp_map.v", family_opt));
} else {
run("alumacc");
}
@ -274,7 +274,7 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("map_cells")) {
if (iopads || help_mode)
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)");
run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt));
run("clean -purge");
}
@ -294,7 +294,7 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("vpr")) {
if (!blif_file.empty() || help_mode) {
run(stringf("opt_clean -purge"));
run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file));
}
}
}

20
techlibs/intel_alm/synth_intel_alm.cc
View file

@ -169,17 +169,17 @@ struct SynthIntelALMPass : public ScriptPass {
if (check_label("begin")) {
if (family_opt == "cyclonev")
run(stringf("read_verilog -sv -lib +/intel_alm/%s/cells_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt.c_str()));
run(stringf("read_verilog -sv -lib +/intel_alm/%s/cells_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt));
run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt));
// Misc and common cells
run("read_verilog -lib +/intel/common/altpll_bb.v");
run("read_verilog -lib +/intel_alm/common/megafunction_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("coarse")) {
@ -225,8 +225,8 @@ struct SynthIntelALMPass : public ScriptPass {
}
if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type.c_str()));
run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type));
run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type));
}
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {

10
techlibs/lattice/synth_lattice.cc
View file

@ -333,7 +333,7 @@ struct SynthLatticePass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib -specify +/lattice/cells_sim" + postfix + ".v +/lattice/cells_bb" + postfix + ".v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("coarse"))
@ -449,9 +449,9 @@ struct SynthLatticePass : public ScriptPass
abc9_opts += " -maxlut 4";
std::string k = "synth_lattice.abc9.W";
if (active_design && active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k));
else
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k));
if (nowidelut)
abc9_opts += " -maxlut 4";
if (dff)
@ -489,13 +489,13 @@ struct SynthLatticePass : public ScriptPass
if (check_label("edif"))
{
if (!edif_file.empty() || help_mode)
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file));
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthLatticePass;

8
techlibs/microchip/synth_microchip.cc
View file

@ -262,7 +262,7 @@ struct SynthMicrochipPass : public ScriptPass {
read_args += " -lib -specify +/microchip/cells_sim.v";
run("read_verilog" + read_args);
run(stringf("hierarchy -check %s", top_opt.c_str()));
run(stringf("hierarchy -check %s", top_opt));
}
if (check_label("prepare")) {
@ -534,18 +534,18 @@ struct SynthMicrochipPass : public ScriptPass {
if (check_label("edif")) {
if (!edif_file.empty() || help_mode)
run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
run(stringf("write_edif -pvector bra %s", edif_file));
}
if (check_label("blif")) {
if (!blif_file.empty() || help_mode)
run(stringf("write_blif %s", blif_file.c_str()));
run(stringf("write_blif %s", blif_file));
}
if (check_label("vlog"))
{
if (!vlog_file.empty() || help_mode)
run(stringf("write_verilog %s", help_mode ? "<file-name>" : vlog_file.c_str()));
run(stringf("write_verilog %s", help_mode ? "<file-name>" : vlog_file));
}
}
} SynthMicrochipPass;

8
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -244,7 +244,7 @@ struct SynthNanoXplorePass : public ScriptPass
run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim" + postfix + ".v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
run("techmap -map +/nanoxplore/cells_wrap.v");
run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("coarse"))
@ -335,9 +335,9 @@ struct SynthNanoXplorePass : public ScriptPass
std::string abc9_opts = " -maxlut 4";
std::string k = "synth_nanoxplore.abc9.W";
if (active_design && active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k));
else
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k));
run("abc9" + abc9_opts);
} else {
std::string abc_args = " -dress";
@ -362,7 +362,7 @@ struct SynthNanoXplorePass : public ScriptPass
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthNanoXplorePass;

10
techlibs/nexus/synth_nexus.cc
View file

@ -254,7 +254,7 @@ struct SynthNexusPass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib -specify +/nexus/cells_sim.v +/nexus/cells_xtra.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("coarse"))
@ -361,9 +361,9 @@ struct SynthNexusPass : public ScriptPass
abc9_opts += " -maxlut 4";
std::string k = "synth_nexus.abc9.W";
if (active_design && active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k));
else
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k));
if (nowidelut)
abc9_opts += " -maxlut 4";
if (dff)
@ -405,13 +405,13 @@ struct SynthNexusPass : public ScriptPass
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
if (check_label("vm"))
{
if (!vm_file.empty() || help_mode)
run(stringf("write_verilog %s", help_mode ? "<file-name>" : vm_file.c_str()));
run(stringf("write_verilog %s", help_mode ? "<file-name>" : vm_file));
}
}
} SynthNexusPass;

14
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -198,16 +198,16 @@ struct SynthQuickLogicPass : public ScriptPass {
}
if (check_label("begin")) {
std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path.c_str(), lib_path.c_str(), family.c_str());
std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path, lib_path, family);
if (family == "qlf_k6n10f") {
read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path.c_str());
read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path);
if (bramTypes)
read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path.c_str());
read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path);
if (dsp)
read_simlibs += stringf(" %sqlf_k6n10f/dsp_sim.v", lib_path.c_str());
read_simlibs += stringf(" %sqlf_k6n10f/dsp_sim.v", lib_path);
}
run(read_simlibs);
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("prepare")) {
@ -373,13 +373,13 @@ struct SynthQuickLogicPass : public ScriptPass {
if (check_label("blif", "(if -blif)")) {
if (!blif_file.empty() || help_mode) {
run(stringf("write_blif -attr -param %s %s", top_opt.c_str(), blif_file.c_str()));
run(stringf("write_blif -attr -param %s %s", top_opt, blif_file));
}
}
if (check_label("verilog", "(if -verilog)")) {
if (!verilog_file.empty() || help_mode) {
run(stringf("write_verilog -noattr -nohex %s", help_mode ? "<file-name>" : verilog_file.c_str()));
run(stringf("write_verilog -noattr -nohex %s", help_mode ? "<file-name>" : verilog_file));
}
}
}

8
techlibs/sf2/synth_sf2.cc
View file

@ -166,7 +166,7 @@ struct SynthSf2Pass : public ScriptPass
if (check_label("begin"))
{
run("read_verilog -lib +/sf2/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
@ -244,19 +244,19 @@ struct SynthSf2Pass : public ScriptPass
if (check_label("edif"))
{
if (!edif_file.empty() || help_mode)
run(stringf("write_edif -gndvccy %s", help_mode ? "<file-name>" : edif_file.c_str()));
run(stringf("write_edif -gndvccy %s", help_mode ? "<file-name>" : edif_file));
}
if (check_label("vlog"))
{
if (!vlog_file.empty() || help_mode)
run(stringf("write_verilog %s", help_mode ? "<file-name>" : vlog_file.c_str()));
run(stringf("write_verilog %s", help_mode ? "<file-name>" : vlog_file));
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthSf2Pass;

14
techlibs/xilinx/synth_xilinx.cc
View file

@ -350,7 +350,7 @@ struct SynthXilinxPass : public ScriptPass
run("read_verilog -lib +/xilinx/cells_xtra.v");
run(stringf("hierarchy -check %s", top_opt.c_str()));
run(stringf("hierarchy -check %s", top_opt));
}
if (check_label("prepare")) {
@ -649,10 +649,10 @@ struct SynthXilinxPass : public ScriptPass
std::string abc9_opts;
std::string k = "synth_xilinx.abc9.W";
if (active_design && active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k));
else {
k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
k = stringf("synth_xilinx.abc9.%s.W", family);
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")));
}
if (nowidelut)
abc9_opts += stringf(" -maxlut %d", lut_size);
@ -718,18 +718,18 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("edif")) {
if (!edif_file.empty() || help_mode)
run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
run(stringf("write_edif -pvector bra %s", edif_file));
}
if (check_label("blif")) {
if (!blif_file.empty() || help_mode)
run(stringf("write_blif %s", blif_file.c_str()));
run(stringf("write_blif %s", blif_file));
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
} SynthXilinxPass;