"Reduce port resize to warning" changed the resize message from
log_warning() to log(), which -q suppresses. Run the resize case without
-q and drop the stale "Warning: " prefix so the message is observed.
Co-authored-by: Cursor <cursoragent@cursor.com>
The tests/silimate suite (which aborted the Run tests CI job) exposed two
issues in the generalized passes:
- opt_compact_prefix: the forward dense pack regressions at 64 and 128 bits
no longer rewrote. The ConstEval fingerprint was uint64_t-based (capped at
62 bits) and the per-cone cell cap (max_width*96) was below the O(width^2)
cell count of a wide pack. The fingerprint now drives whole-width Const
bit patterns (no width cap) and the cone cap scales quadratically; total
work stays bounded by the shared walk/eval budgets.
- opt_priority_onehot: the "max-width below lane count" negative test set
max_width=8 on a 16-lane design expecting no rewrite, but the generalized
matcher legitimately (and equivalence-provably) rewrites the 8-lane
sub-region. The test now uses max_width=3 (below min_width 4) to verify
the width gate suppresses all matching.
Co-authored-by: Cursor <cursoragent@cursor.com>
- update CMakeLists.txt to load two new files:
- SilimateConfig.cmake: sets Silimate configuration options and defaults
- SilimateVerific.cmake: compiles Verific library, optionally with Silimate modifications
- include silimate tests in test Makefile
Rewrite power-of-two indexed word selects to $bmux when the shift
amount already carries the scale as low zero bits.
Keep the rule to non-overlapping selections and bound the generated
mux ways. Add regressions for aligned shifts, padding, signed
extension, and shiftmul handoff cases.
Comes with a set of tests which (currently) pass with `read_verilog` but fail with `verific` based on #5878.
Add `--check-sv`, an alternative to `--prove-sv` with generator defined yosys commands. Helpful for when you want to run the same set of commands on a bunch of sv files.
