Fix opt_compact_prefix up

tests/silimate/opt_compact_prefix.ys

@@ -114,6 +114,23 @@ select -assert-count 32 t:$gt
 design -reset
 log -pop
 
+log -header "Renamed ports: forward dense pack"
+log -push
+design -reset
+verific -cfg veri_optimize_wide_selector 1
+verific -cfg db_infer_wide_muxes_post_elaboration 0
+read -sv opt_compact_prefix_renamed.sv
+verific -import opt_compact_prefix_pack_renamed
+proc; opt_clean
+opt_compact_prefix
+opt_clean
+select -assert-none t:$shl
+select -assert-none t:$mux
+select -assert-count 7 t:$add
+select -assert-count 8 t:$gt
+design -reset
+log -pop
+
 log -header "Exact regression size: 16-entry reverse suffix read"
 log -push
 design -reset
@@ -131,6 +148,53 @@ select -assert-min 1 t:$eq
 design -reset
 log -pop
 
+log -header "Renamed ports: reverse suffix read"
+log -push
+design -reset
+verific -cfg veri_optimize_wide_selector 1
+verific -cfg db_infer_wide_muxes_post_elaboration 0
+read -sv opt_compact_prefix_renamed.sv
+verific -import opt_compact_prefix_sub_renamed
+proc; opt_clean
+opt_compact_prefix
+opt_clean
+select -assert-none t:$sub
+select -assert-none t:$mux
+select -assert-min 1 t:$add
+select -assert-min 1 t:$eq
+design -reset
+log -pop
+
+log -header "Yosys frontend: forward dense pack"
+log -push
+design -reset
+read_verilog -sv opt_compact_prefix_yosys_frontend.v
+hierarchy -top opt_compact_prefix_yosys_pack
+proc; opt_clean
+opt_compact_prefix
+opt_clean
+select -assert-none t:$shl
+select -assert-none t:$mux
+select -assert-count 7 t:$add
+select -assert-count 8 t:$gt
+design -reset
+log -pop
+
+log -header "Yosys frontend: reverse suffix read"
+log -push
+design -reset
+read_verilog -sv opt_compact_prefix_yosys_frontend.v
+hierarchy -top opt_compact_prefix_yosys_sub
+proc; opt_clean
+opt_compact_prefix
+opt_clean
+select -assert-none t:$sub
+select -assert-none t:$mux
+select -assert-min 1 t:$add
+select -assert-min 1 t:$eq
+design -reset
+log -pop
+
 log -header "Reverse suffix read with add-by-minus-one decrement"
 log -push
 design -reset

tests/silimate/opt_compact_prefix_renamed.sv

@@ -0,0 +1,32 @@
+module opt_compact_prefix_pack_renamed (
+  input  logic [7:0] in_bits,
+  output logic [7:0] packed_bits
+);
+  always_comb begin
+    packed_bits = '0;
+    for (int I = 0, indx = 0; I < 8; I++) begin
+      if (in_bits[I]) begin
+        packed_bits[indx] = in_bits[I];
+        indx += 1;
+      end
+    end
+  end
+endmodule
+
+module opt_compact_prefix_sub_renamed (
+  input  logic [15:0] stall_vec,
+  input  logic [15:0] payload_vec,
+  output logic [15:0] allow_mask
+);
+  always_comb begin
+    allow_mask = '0;
+    for (int I = 8, indx = 8; I > 0; I--) begin
+      if (stall_vec[I-1]) begin
+        allow_mask[I-1] = 1'b0;
+      end else begin
+        allow_mask[I-1] = payload_vec[indx-1];
+        indx = indx - 1;
+      end
+    end
+  end
+endmodule

tests/silimate/opt_compact_prefix_yosys_frontend.v

@@ -0,0 +1,38 @@
+module opt_compact_prefix_yosys_pack (
+  input  wire [7:0] in_bits,
+  output reg  [7:0] packed_bits
+);
+  integer I;
+  integer indx;
+  always @* begin
+    packed_bits = 8'b0;
+    indx = 0;
+    for (I = 0; I < 8; I = I + 1) begin
+      if (in_bits[I]) begin
+        packed_bits[indx] = in_bits[I];
+        indx = indx + 1;
+      end
+    end
+  end
+endmodule
+
+module opt_compact_prefix_yosys_sub (
+  input  wire [15:0] stall_vec,
+  input  wire [15:0] payload_vec,
+  output reg  [15:0] allow_mask
+);
+  integer I;
+  integer indx;
+  always @* begin
+    allow_mask = 16'b0;
+    indx = 8;
+    for (I = 8; I > 0; I = I - 1) begin
+      if (stall_vec[I-1]) begin
+        allow_mask[I-1] = 1'b0;
+      end else begin
+        allow_mask[I-1] = payload_vec[indx-1];
+        indx = indx - 1;
+      end
+    end
+  end
+endmodule