mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-18 21:25:47 +00:00
Merge branch 'main' into opt_addcin
This commit is contained in:
Akash Levy
commit
5c3fbd2d63
11 changed files with 1505 additions and 8 deletions
116
tests/silimate/ffnormpol.ys
Normal file
116
tests/silimate/ffnormpol.ys
Normal file
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@ -0,0 +1,116 @@
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log -header "Normalize coarse and fine FF/latch polarities"
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log -push
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design -reset
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read_rtlil <<EOT
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module \top
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wire input 1 \clk
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wire input 2 \en
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wire input 3 \arst
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wire input 4 \srst
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wire input 5 \aload
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wire width 2 input 6 \set
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wire width 2 input 7 \clr
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wire width 2 input 8 \d
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wire width 2 input 9 \ad
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wire width 2 output 10 \q_dffe
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wire width 2 output 11 \q_adffe
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wire width 2 output 12 \q_sdffce
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wire width 2 output 13 \q_aldffe
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wire width 2 output 14 \q_dlatchsr
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wire width 2 output 15 \q_sr
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wire output 16 \q_fine
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cell $dffe \dffe_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \D \d
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connect \Q \q_dffe
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end
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cell $adffe \adffe_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \ARST_POLARITY 1'0
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parameter \ARST_VALUE 2'01
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \ARST \arst
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connect \D \d
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connect \Q \q_adffe
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end
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cell $sdffce \sdffce_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \SRST_POLARITY 1'0
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parameter \SRST_VALUE 2'10
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \SRST \srst
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connect \D \d
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connect \Q \q_sdffce
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end
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cell $aldffe \aldffe_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \ALOAD_POLARITY 1'0
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \ALOAD \aload
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connect \D \d
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connect \AD \ad
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connect \Q \q_aldffe
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end
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cell $dlatchsr \dlatchsr_neg
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parameter \EN_POLARITY 1'0
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parameter \SET_POLARITY 1'0
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parameter \CLR_POLARITY 1'0
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parameter \WIDTH 2
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connect \EN \aload
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connect \SET \set
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connect \CLR \clr
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connect \D \d
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connect \Q \q_dlatchsr
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end
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cell $sr \sr_neg
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parameter \SET_POLARITY 1'0
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parameter \CLR_POLARITY 1'0
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parameter \WIDTH 2
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connect \SET \set
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connect \CLR \clr
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connect \Q \q_sr
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end
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cell $_DFFE_NN_ \fine_dffe_neg
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connect \C \clk
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connect \E \en
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connect \D \d [0]
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connect \Q \q_fine
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end
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end
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EOT
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ffnormpol
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check -assert
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select -assert-count 0 r:CLK_POLARITY=0
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select -assert-count 0 r:EN_POLARITY=0
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select -assert-count 0 r:ARST_POLARITY=0
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select -assert-count 0 r:SRST_POLARITY=0
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select -assert-count 0 r:ALOAD_POLARITY=0
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select -assert-count 0 r:SET_POLARITY=0
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select -assert-count 0 r:CLR_POLARITY=0
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select -assert-count 1 t:$_DFFE_PP_
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select -assert-count 7 t:$not
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design -reset
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log -pop
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188
tests/silimate/infer_icg.ys
Normal file
188
tests/silimate/infer_icg.ys
Normal file
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@ -0,0 +1,188 @@
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log -header "Infer $icg from latch-based clock gate with scan enable"
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log -push
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design -reset
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||||
read_verilog -sv <<EOF
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module top(input logic CK, EN, SE, output logic Q);
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logic en_ff;
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logic enable;
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assign enable = EN | SE;
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always_latch
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if (!CK)
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en_ff = enable;
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assign Q = CK & en_ff;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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select -assert-count 1 t:$dlatch
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select -assert-count 1 t:$and t:$logic_and
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select -assert-count 1 t:$or t:$logic_or
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select -assert-count 0 t:$icg
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$and t:$logic_and
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select -assert-count 0 t:$or t:$logic_or
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design -reset
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log -pop
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log -header "Infer $icg from latch-based clock gate without scan enable"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, output logic Q);
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logic en_ff;
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always_latch
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if (!CK)
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en_ff = EN;
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assign Q = en_ff & CK;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$and t:$logic_and
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design -reset
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log -pop
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log -header "Infer $icg from active-high latch on inverted clock"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, SE, output logic Q);
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logic en_ff;
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logic enable;
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logic nCK;
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assign enable = EN | SE;
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assign nCK = !CK;
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always_latch
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if (nCK)
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en_ff = enable;
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assign Q = CK & en_ff;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$and t:$logic_and
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select -assert-count 0 t:$or t:$logic_or
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design -reset
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log -pop
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log -header "Infer $icg from active-high latch on inverted clock without scan enable"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, output logic Q);
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logic en_ff;
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logic nCK;
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assign nCK = !CK;
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always_latch
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if (nCK)
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en_ff = EN;
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assign Q = CK & en_ff;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$and t:$logic_and
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design -reset
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log -pop
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log -header "Infer $icg from high-idle OR clock gate"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, SE, output logic Q);
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logic en_ff;
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logic enable;
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assign enable = EN | SE;
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always_latch
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if (CK)
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en_ff = enable;
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assign Q = CK | !en_ff;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$or t:$logic_or
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design -reset
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log -pop
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log -header "Infer $icg from high-idle OR clock gate without scan enable"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, output logic Q);
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logic en_ff;
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always_latch
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if (CK)
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en_ff = EN;
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assign Q = CK | !en_ff;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$or t:$logic_or
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design -reset
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log -pop
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117
tests/various/opt_andor_pmux.v
Normal file
117
tests/various/opt_andor_pmux.v
Normal file
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@ -0,0 +1,117 @@
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module andor_pmux_basic (
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input [2:0] sel,
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input [5:0] d,
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input a,
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output [1:0] y
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);
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assign y = ({2{sel == 3'd1}} & d[1:0]) |
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({2{sel == 3'd3}} & {d[2] & a, d[3]}) |
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({2{sel == 3'd6}} & 2'b01);
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endmodule
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|
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module andor_pmux_outer_enable (
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input [2:0] sel,
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input [3:0] d,
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input en,
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output [1:0] y
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);
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wire [1:0] body;
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assign body = ({2{sel == 3'd2}} & {1'b0, d[0]}) |
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({2{sel == 3'd5}} & {d[1], d[2]}) |
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({2{sel == 3'd7}} & {d[3], 1'b1});
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assign y = {2{en}} & body;
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endmodule
|
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|
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module andor_pmux_duplicate (
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input [1:0] sel,
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input a,
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input b,
|
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input c,
|
||||
input d,
|
||||
input e,
|
||||
input f,
|
||||
output [1:0] y
|
||||
);
|
||||
assign y = ({2{sel == 2'd1}} & {a, b}) |
|
||||
({2{sel == 2'd1}} & {c, d}) |
|
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({2{sel == 2'd2}} & {e, f});
|
||||
endmodule
|
||||
|
||||
module andor_pmux_mixed_select_negative (
|
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input [1:0] sel_a,
|
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input [1:0] sel_b,
|
||||
input a,
|
||||
input b,
|
||||
output y
|
||||
);
|
||||
assign y = ((sel_a == 2'd1) & a) |
|
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((sel_b == 2'd2) & b);
|
||||
endmodule
|
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|
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module andor_pmux_wide_decode (
|
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input [3:0] sel,
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input [23:0] d,
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input q,
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output [3:0] y
|
||||
);
|
||||
assign y = ({4{sel == 4'd1}} & d[3:0]) |
|
||||
({4{sel == 4'd4}} & {d[4] & q, d[5], 1'b0, d[6]}) |
|
||||
({4{sel == 4'd7}} & d[10:7]) |
|
||||
({4{sel == 4'd9}} & {1'b1, d[11], d[12] & q, d[13]}) |
|
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({4{sel == 4'd12}} & d[17:14]) |
|
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({4{sel == 4'd15}} & {d[18], d[19], d[20], 1'b1});
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||||
endmodule
|
||||
|
||||
module andor_pmux_shared_subtree (
|
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input [2:0] sel,
|
||||
input [3:0] d,
|
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input q,
|
||||
output y,
|
||||
output z
|
||||
);
|
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wire sub = ((sel == 3'd1) & d[0]) |
|
||||
((sel == 3'd3) & d[1]);
|
||||
|
||||
assign y = sub | ((sel == 3'd6) & d[2]);
|
||||
assign z = sub & q;
|
||||
endmodule
|
||||
|
||||
module andor_pmux_single_arm_negative (
|
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input [1:0] sel,
|
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input [1:0] d,
|
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output [1:0] y
|
||||
);
|
||||
assign y = ({2{sel == 2'd1}} & d) | 2'b00;
|
||||
endmodule
|
||||
|
||||
module andor_pmux_all_zero_negative (
|
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input [1:0] sel,
|
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output [1:0] y
|
||||
);
|
||||
assign y = ({2{sel == 2'd1}} & 2'b00) |
|
||||
({2{sel == 2'd2}} & 2'b00);
|
||||
endmodule
|
||||
|
||||
module andor_pmux_non_eq_leaf_negative (
|
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input [1:0] sel,
|
||||
input raw,
|
||||
input a,
|
||||
input b,
|
||||
output y
|
||||
);
|
||||
assign y = ((sel == 2'd1) & a) |
|
||||
(raw & b);
|
||||
endmodule
|
||||
|
||||
module andor_pmux_duplicate_complex (
|
||||
input [2:0] sel,
|
||||
input [8:0] d,
|
||||
input q,
|
||||
input r,
|
||||
output [2:0] y
|
||||
);
|
||||
assign y = ({3{sel == 3'd2}} & {d[0] & q, d[1], d[2]}) |
|
||||
({3{sel == 3'd2}} & {d[3], d[4] & r, d[5]}) |
|
||||
({3{sel == 3'd5}} & {d[6], d[7] & q, d[8] & r});
|
||||
endmodule
|
||||
152
tests/various/opt_andor_pmux.ys
Normal file
152
tests/various/opt_andor_pmux.ys
Normal file
|
|
@ -0,0 +1,152 @@
|
|||
read_verilog opt_andor_pmux.v
|
||||
design -save read
|
||||
|
||||
design -load read
|
||||
hierarchy -top andor_pmux_basic
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save gold
|
||||
opt_andor_pmux
|
||||
opt_clean
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top andor_pmux_wide_decode
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save gold
|
||||
opt_andor_pmux
|
||||
opt_clean
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top andor_pmux_shared_subtree
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save gold
|
||||
opt_andor_pmux
|
||||
opt_clean
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top andor_pmux_single_arm_negative
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save gold
|
||||
opt_andor_pmux
|
||||
opt_clean
|
||||
select -assert-count 0 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top andor_pmux_all_zero_negative
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save gold
|
||||
opt_andor_pmux
|
||||
opt_clean
|
||||
select -assert-count 0 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top andor_pmux_non_eq_leaf_negative
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save gold
|
||||
opt_andor_pmux
|
||||
opt_clean
|
||||
select -assert-count 0 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top andor_pmux_duplicate_complex
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save gold
|
||||
opt_andor_pmux
|
||||
opt_clean
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top andor_pmux_outer_enable
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save gold
|
||||
opt_andor_pmux
|
||||
opt_clean
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top andor_pmux_duplicate
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save gold
|
||||
opt_andor_pmux
|
||||
opt_clean
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top andor_pmux_mixed_select_negative
|
||||
proc
|
||||
opt_expr
|
||||
opt_clean
|
||||
design -save gold
|
||||
opt_andor_pmux
|
||||
opt_clean
|
||||
select -assert-count 0 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
Loading…
Add table
Add a link
Reference in a new issue