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Add opt_compact_prefix pass

This commit is contained in:
Akash Levy 2026-06-01 23:00:33 -07:00
parent d1ec970f86
commit a730032f5f
11 changed files with 995 additions and 0 deletions

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# Tests for opt_compact_prefix.
log -header "Forward dense pack self-equivalence"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_pack.sv
verific -import opt_compact_prefix_pack
proc; opt_clean
rename opt_compact_prefix_pack gold
read -sv opt_compact_prefix_pack.sv
verific -import opt_compact_prefix_pack
proc; opt_clean
opt_compact_prefix
opt_clean
rename opt_compact_prefix_pack gate
miter -equiv -flatten -make_assert gold gate miter
hierarchy -top miter
proc; opt; memory; opt
sat -prove-asserts -verify
design -reset
log -pop
log -header "Forward dense pack structural rewrite"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_pack.sv
verific -import opt_compact_prefix_pack
proc; opt_clean
opt_compact_prefix
opt_clean
select -assert-none t:$shl
select -assert-none t:$mux
select -assert-count 7 t:$add
select -assert-count 8 t:$gt
design -reset
log -pop
log -header "Reverse suffix read self-equivalence"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_sub.sv
verific -import opt_compact_prefix_sub
proc; opt_clean
rename opt_compact_prefix_sub gold
read -sv opt_compact_prefix_sub.sv
verific -import opt_compact_prefix_sub
proc; opt_clean
opt_compact_prefix
opt_clean
rename opt_compact_prefix_sub gate
miter -equiv -flatten -make_assert gold gate miter
hierarchy -top miter
proc; opt; memory; opt
sat -prove-asserts -verify
design -reset
log -pop
log -header "Reverse suffix read structural rewrite"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_sub.sv
verific -import opt_compact_prefix_sub
proc; opt_clean
opt_compact_prefix
opt_clean
select -assert-none t:$sub
select -assert-none t:$mux
select -assert-min 1 t:$add
select -assert-min 1 t:$eq
design -reset
log -pop
log -header "Negative: unrelated mux module unchanged"
log -push
design -reset
read_verilog <<EOF
module top(input wire sel, input wire [7:0] a, b, output wire [7:0] y);
assign y = sel ? a : b;
endmodule
EOF
proc; opt_clean
select -assert-count 1 t:$mux
opt_compact_prefix
select -assert-count 1 t:$mux
design -reset
log -pop
log -header "Exact regression size: 32-bit forward dense pack"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_pack32.sv
verific -import opt_compact_prefix_pack32
proc; opt_clean
opt_compact_prefix
opt_clean
select -assert-none t:$shl
select -assert-none t:$mux
select -assert-count 31 t:$add
select -assert-count 32 t:$gt
design -reset
log -pop
log -header "Exact regression size: 16-entry reverse suffix read"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_sub16.sv
verific -import opt_compact_prefix_sub16
proc; opt_clean
opt_compact_prefix
opt_clean
select -assert-none t:$sub
select -assert-none t:$mux
select -assert-min 1 t:$add
select -assert-min 1 t:$eq
design -reset
log -pop
log -header "Reverse suffix read with add-by-minus-one decrement"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_addneg.sv
verific -import opt_compact_prefix_addneg
proc; opt_clean
rename opt_compact_prefix_addneg gold
read -sv opt_compact_prefix_addneg.sv
verific -import opt_compact_prefix_addneg
proc; opt_clean
opt_compact_prefix
opt_clean
rename opt_compact_prefix_addneg gate
miter -equiv -flatten -make_assert gold gate miter
hierarchy -top miter
proc; opt; memory; opt
sat -prove-asserts -verify
design -reset
log -pop
log -header "Max width: forward pack left unchanged"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_pack32.sv
verific -import opt_compact_prefix_pack32
proc; opt_clean
select -assert-min 1 t:$shl
opt_compact_prefix -max_width 8
select -assert-min 1 t:$shl
select -assert-none w:*compact*
design -reset
log -pop
log -header "Max width: reverse suffix read left unchanged"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_sub16.sv
verific -import opt_compact_prefix_sub16
proc; opt_clean
select -assert-min 1 t:$sub
opt_compact_prefix -max_width 8
select -assert-min 1 t:$sub
select -assert-none w:*compact*
design -reset
log -pop
log -header "Negative near miss: same port names passthrough"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_near_miss.sv
verific -import opt_compact_prefix_pack_passthrough
proc; opt_clean
opt_compact_prefix
select -assert-none w:*compact*
design -reset
log -pop
log -header "Negative near miss: same port names nonzero pack init"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_near_miss.sv
verific -import opt_compact_prefix_pack_nonzero_init
proc; opt_clean
opt_compact_prefix
select -assert-none w:*compact*
design -reset
log -pop
log -header "Negative near miss: same port names non-unit pack stride"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_near_miss.sv
verific -import opt_compact_prefix_pack_stride2
proc; opt_clean
opt_compact_prefix
select -assert-none w:*compact*
design -reset
log -pop
log -header "Negative near miss: same port names nonzero reverse init"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_near_miss.sv
verific -import opt_compact_prefix_sub_nonzero_init
proc; opt_clean
opt_compact_prefix
select -assert-none w:*compact*
design -reset
log -pop
log -header "Scaling: 64-bit forward pack"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_scale.sv
verific -import opt_compact_prefix_pack64
proc; opt_clean
opt_compact_prefix
opt_clean
select -assert-none t:$shl
select -assert-none t:$mux
select -assert-count 63 t:$add
select -assert-count 64 t:$gt
design -reset
log -pop
log -header "Scaling: 128-bit forward pack with explicit max_width"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_scale.sv
verific -import opt_compact_prefix_pack128
proc; opt_clean
opt_compact_prefix -max_width 128
opt_clean
select -assert-none t:$shl
select -assert-none t:$mux
select -assert-count 127 t:$add
select -assert-count 128 t:$gt
design -reset
log -pop
log -header "Multi-module: only matching module rewrites"
log -push
design -reset
verific -cfg veri_optimize_wide_selector 1
verific -cfg db_infer_wide_muxes_post_elaboration 0
read -sv opt_compact_prefix_multi.sv
verific -import opt_compact_prefix_multi_match opt_compact_prefix_multi_keep
proc; opt_clean
opt_compact_prefix
opt_clean
select -assert-none opt_compact_prefix_multi_match/t:$shl
select -assert-none opt_compact_prefix_multi_match/t:$mux
select -assert-count 1 opt_compact_prefix_multi_keep/t:$mux
design -reset
log -pop

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module opt_compact_prefix_addneg (
input logic [15:0] disable_in,
input logic [15:0] data_in,
output logic [15:0] mask
);
always_comb begin
mask = '0;
for (int I = 8, indx = 8; I > 0; I--) begin
if (disable_in[I-1]) begin
mask[I-1] = 1'b0;
end else begin
mask[I-1] = data_in[indx-1];
indx = indx + -1;
end
end
end
endmodule

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module opt_compact_prefix_multi_match (
input logic [7:0] sig,
output logic [7:0] sig2
);
always_comb begin
sig2 = '0;
for (int I = 0, indx = 0; I < 8; I++) begin
if (sig[I]) begin
sig2[indx] = sig[I];
indx += 1;
end
end
end
endmodule
module opt_compact_prefix_multi_keep (
input logic sel,
input logic [7:0] a,
input logic [7:0] b,
output logic [7:0] y
);
assign y = sel ? a : b;
endmodule

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module opt_compact_prefix_pack_passthrough (
input logic [7:0] sig,
output logic [7:0] sig2
);
always_comb begin
sig2 = '0;
for (int I = 0; I < 8; I++) begin
if (sig[I])
sig2[I] = sig[I];
end
end
endmodule
module opt_compact_prefix_pack_nonzero_init (
input logic [7:0] sig,
output logic [7:0] sig2
);
always_comb begin
sig2 = '1;
for (int I = 0, indx = 0; I < 8; I++) begin
if (sig[I]) begin
sig2[indx] = sig[I];
indx += 1;
end
end
end
endmodule
module opt_compact_prefix_pack_stride2 (
input logic [7:0] sig,
output logic [7:0] sig2
);
always_comb begin
sig2 = '0;
for (int I = 0, indx = 0; I < 4; I++) begin
if (sig[I]) begin
sig2[indx] = sig[I];
indx += 2;
end
end
end
endmodule
module opt_compact_prefix_sub_nonzero_init (
input logic [15:0] disable_in,
input logic [15:0] data_in,
output logic [15:0] mask
);
always_comb begin
mask = '1;
for (int I = 8, indx = 8; I > 0; I--) begin
if (disable_in[I-1]) begin
mask[I-1] = 1'b0;
end else begin
mask[I-1] = data_in[indx-1];
indx = indx - 1;
end
end
end
endmodule
module opt_compact_prefix_sub_stride2 (
input logic [15:0] disable_in,
input logic [15:0] data_in,
output logic [15:0] mask
);
always_comb begin
mask = '0;
for (int I = 8, indx = 16; I > 0; I--) begin
if (disable_in[I-1]) begin
mask[I-1] = 1'b0;
end else begin
mask[I-1] = data_in[indx-1];
indx = indx - 2;
end
end
end
endmodule

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module opt_compact_prefix_pack (
input logic [7:0] sig,
output logic [7:0] sig2
);
always_comb begin
sig2 = '0;
for (int I = 0, indx = 0; I < 8; I++) begin
if (sig[I]) begin
sig2[indx] = sig[I];
indx += 1;
end
end
end
endmodule

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module opt_compact_prefix_pack32 (
input logic [31:0] sig,
output logic [31:0] sig2
);
always_comb begin
sig2 = '0;
for (int I = 0, indx = 0; I < 32; I++) begin
if (sig[I]) begin
sig2[indx] = sig[I];
indx += 1;
end
end
end
endmodule

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module opt_compact_prefix_pack64 (
input logic [63:0] sig,
output logic [63:0] sig2
);
always_comb begin
sig2 = '0;
for (int I = 0, indx = 0; I < 64; I++) begin
if (sig[I]) begin
sig2[indx] = sig[I];
indx += 1;
end
end
end
endmodule
module opt_compact_prefix_pack128 (
input logic [127:0] sig,
output logic [127:0] sig2
);
always_comb begin
sig2 = '0;
for (int I = 0, indx = 0; I < 128; I++) begin
if (sig[I]) begin
sig2[indx] = sig[I];
indx += 1;
end
end
end
endmodule

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module opt_compact_prefix_sub (
input logic [15:0] disable_in,
input logic [15:0] data_in,
output logic [15:0] mask
);
always_comb begin
mask = '0;
for (int I = 8, indx = 8; I > 0; I--) begin
if (disable_in[I-1]) begin
mask[I-1] = 1'b0;
end else begin
mask[I-1] = data_in[indx-1];
indx = indx - 1;
end
end
end
endmodule

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module opt_compact_prefix_sub16 (
input logic [31:0] disable_in,
input logic [31:0] data_in,
output logic [31:0] mask
);
always_comb begin
mask = '0;
for (int I = 16, indx = 16; I > 0; I--) begin
if (disable_in[I-1]) begin
mask[I-1] = 1'b0;
end else begin
mask[I-1] = data_in[indx-1];
indx = indx - 1;
end
end
end
endmodule