1941 commits

Author	SHA1	Message	Date
Clifford Wolf	bd65e67d8a	Improvements in satgen undef handling	2013-11-25 15:12:01 +01:00
Clifford Wolf	8c3f4b3957	Started implementing undef handling in satgen	2013-11-25 04:51:33 +01:00
Clifford Wolf	76f7c10cfc	Using simplemap mappers from techmap	2013-11-24 23:31:14 +01:00
Clifford Wolf	3ee33cbdaf	Added simplemap pass	2013-11-24 22:52:30 +01:00
Clifford Wolf	8dafecd34d	Added module->avail_parameters (for advanced techmap features)	2013-11-24 20:29:07 +01:00
Clifford Wolf	4011d47646	Added techmap -D and -I options	2013-11-24 20:04:48 +01:00
Clifford Wolf	20175afd29	Added "techmap -share_map" option	2013-11-24 19:50:25 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	72b35e0b99	Fixed "flatten" top-module detection: Only use on fully selected designs	2013-11-24 14:10:46 +01:00
Clifford Wolf	28093d9dd2	Added "top" attribute to mark top module in hierarchy	2013-11-24 05:03:43 +01:00
Clifford Wolf	5f9c7fc6ea	Improved handling of techmap special wires	2013-11-23 16:49:58 +01:00
Clifford Wolf	532091afcb	Added more generic _TECHMAP_ wire mechanism to techmap pass	2013-11-23 15:58:06 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	1c4a6411af	Updated abc	2013-11-21 22:39:10 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	84ced2bb8e	Fixed a bug in "add -global_input"	2013-11-21 03:01:20 +01:00
Clifford Wolf	64a5f8f75e	Added "proc_arst -global_arst" feature	2013-11-20 21:00:43 +01:00
Clifford Wolf	2279b2a196	Added "add" command (only wires for now)	2013-11-20 19:37:40 +01:00
Clifford Wolf	63285b300c	Renamed temp module generated by "abc" pass from "logic" to "netlist"	2013-11-19 01:03:57 +01:00
Clifford Wolf	a694324a75	Fixed abc pass blif parser for constant bits	2013-11-13 15:46:28 +01:00
Clifford Wolf	e5b974fa2a	Cleanups and bugfixes in response to new internal cell checker	2013-11-11 00:39:45 +01:00
Clifford Wolf	378cc509cd	Call internal checker more often	2013-11-10 23:24:21 +01:00
Clifford Wolf	223892ac28	Improved user-friendliness of "sat" and "eval" expression parsing	2013-11-09 12:02:27 +01:00
Clifford Wolf	18f9477e95	Added verification of SAT model to "eval -vloghammer_report" command	2013-11-09 11:38:17 +01:00
Clifford Wolf	b04051a0e2	Fixed keep attribute on wires in opt_clean	2013-11-08 05:20:15 +01:00
Clifford Wolf	947bd9b96b	Renamed extend_un0() to extend_u0() and use it in genrtlil	2013-11-07 18:17:10 +01:00
Clifford Wolf	0e1661f84e	Fixed type of sign extension in opt_const $eq/$ne handling	2013-11-07 16:53:28 +01:00
Clifford Wolf	db42a8f89b	Fixed $eq/$ne bitwise optimization in opt_const	2013-11-07 11:54:59 +01:00
Clifford Wolf	f485962c5e	Added handling of unconnected/unspecified signals to eval -vloghammer_report	2013-11-06 22:42:07 +01:00
Clifford Wolf	031a91dc94	Added correct RTL undef handling to eval vloghammer mode	2013-11-06 13:16:47 +01:00
Clifford Wolf	f94266bb42	Added eval -vloghammer_report mode	2013-11-06 04:14:56 +01:00
Clifford Wolf	1d34fd7608	Added support for "keep" attributes on wires	2013-11-05 15:52:29 +01:00
Clifford Wolf	eab536a203	Merge branch 'master' of github.com:cliffordwolf/yosys	2013-11-03 21:13:21 +01:00
Clifford Wolf	f7f0af6f9c	Added resolution of positional arguments to hierarchy pass	2013-11-03 09:42:51 +01:00
Clifford Wolf	0efe16f118	Added placeholder check to dfflibmap and cleaned up some other placeholder checks	2013-10-31 12:27:07 +01:00
Clifford Wolf	b8bfa020fa	Added detection for endless recursion in fsm_detect pass	2013-10-30 00:47:58 +01:00
Clifford Wolf	888c43210b	Fixed help message typo (memory pass)	2013-10-30 00:47:31 +01:00
Clifford Wolf	613750155d	Added -format option to splitnets	2013-10-29 11:01:04 +01:00
Clifford Wolf	ceb971eab9	Added support for i/o buffers to iopadmap	2013-10-26 22:27:40 +02:00
Clifford Wolf	dd56004fc0	Added support for sr flip-flops to dfflibmap	2013-10-24 18:20:06 +02:00
Clifford Wolf	628b994cf6	Added support for complex set-reset flip-flops in proc_dff	2013-10-24 16:54:05 +02:00
Clifford Wolf	e679a5d046	Fixed handling of boolean attributes (passes)	2013-10-24 11:37:54 +02:00
Clifford Wolf	d61699843f	Improved handling of dff with async resets	2013-10-21 14:51:58 +02:00
Clifford Wolf	56ea230676	Added handling of multiple async paths in proc_arst	2013-10-19 00:50:13 +02:00
Clifford Wolf	bfa1a65fa9	Added dffsr support to proc_dff pass	2013-10-18 13:26:52 +02:00
Clifford Wolf	9bc703b964	Improved way of connecting ports in techmap pass	2013-10-17 22:19:38 +02:00
Clifford Wolf	8cc53ef72c	Only prefer connected signals iff they have public names	2013-10-17 22:10:55 +02:00
Clifford Wolf	95dbacefbf	Fixed bug in synthesis of memories that are never written	2013-10-17 21:00:37 +02:00
Clifford Wolf	c20571ca5e	Avoid re-arranging signals on register outputs	2013-10-17 20:48:40 +02:00