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Code Activity

Implemented correct handling of signed module parameters

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This commit is contained in:
Clifford Wolf 2013-11-24 17:17:21 +01:00
parent 1e6836933d
commit 609caa23b5
8 changed files with 19 additions and 8 deletions
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2
passes/hierarchy/hierarchy.cc
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@ -150,7 +150,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox"))
continue;
RTLIL::Module *mod = design->modules[cell->type];
cell->type = mod->derive(design, cell->parameters);
cell->type = mod->derive(design, cell->parameters, cell->signed_parameters);
cell->parameters.clear();
did_something = true;
}

2
passes/techmap/techmap.cc
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@ -239,7 +239,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
tpl = techmap_cache[key];
} else {
if (cell->parameters.size() != 0) {
derived_name = tpl->derive(map, parameters);
derived_name = tpl->derive(map, parameters, cell->signed_parameters);
tpl = map->modules[derived_name];
log_continue = true;
}