mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

Renamed "placeholder" to "blackbox"

Browse source
This commit is contained in:
Clifford Wolf 2013-11-22 15:01:12 +01:00
parent c854ad2e7e
commit 295e352ba6
12 changed files with 27 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/cmds/add.cc
View file

@ -73,7 +73,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
RTLIL::Module *mod = design->modules.at(it.second->type);
if (!design->selected_whole_module(mod->name))
continue;
if (mod->get_bool_attribute("\\placeholder"))
if (mod->get_bool_attribute("\\blackbox"))
continue;
if (it.second->connections.count(name) > 0)
continue;
@ -144,7 +144,7 @@ struct AddPass : public Pass {
RTLIL::Module *module = mod.second;
if (!design->selected_whole_module(module->name))
continue;
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
if (command == "wire")

6
passes/cmds/show.cc
View file

@ -477,8 +477,8 @@ struct ShowWorker
if (!design->selected_module(module->name))
continue;
if (design->selected_whole_module(module->name)) {
if (module->get_bool_attribute("\\placeholder")) {
log("Skipping placeholder module %s.\n", id2cstr(module->name));
if (module->get_bool_attribute("\\blackbox")) {
log("Skipping blackbox module %s.\n", id2cstr(module->name));
continue;
} else
if (module->cells.empty() && module->connections.empty() && module->processes.empty()) {
@ -617,7 +617,7 @@ struct ShowPass : public Pass {
if (format != "ps") {
int modcount = 0;
for (auto &mod_it : design->modules) {
if (mod_it.second->get_bool_attribute("\\placeholder"))
if (mod_it.second->get_bool_attribute("\\blackbox"))
continue;
if (mod_it.second->cells.empty() && mod_it.second->connections.empty())
continue;

6
passes/hierarchy/hierarchy.cc
View file

@ -113,7 +113,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype;
mod->attributes["\\placeholder"] = RTLIL::Const(1);
mod->attributes["\\blackbox"] = RTLIL::Const(1);
design->modules[mod->name] = mod;
for (auto &decl : ports) {
@ -147,7 +147,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
}
if (cell->parameters.size() == 0)
continue;
if (design->modules.at(cell->type)->get_bool_attribute("\\placeholder"))
if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox"))
continue;
RTLIL::Module *mod = design->modules[cell->type];
cell->type = mod->derive(design, cell->parameters);
@ -280,7 +280,7 @@ struct HierarchyPass : public Pass {
log(" use the specified top module to built a design hierarchy. modules\n");
log(" outside this tree (unused modules) are removed.\n");
log("\n");
log("In -generate mode this pass generates placeholder modules for the given cell\n");
log("In -generate mode this pass generates blackbox modules for the given cell\n");
log("types (wildcards supported). For this the design is searched for cells that\n");
log("match the given types and then the given port declarations are used to\n");
log("determine the direction of the ports. The syntax for a port declaration is:\n");

2
passes/techmap/dfflibmap.cc
View file

@ -498,7 +498,7 @@ struct DfflibmapPass : public Pass {
logmap_all();
for (auto &it : design->modules)
if (design->selected(it.second) && !it.second->get_bool_attribute("\\placeholder"))
if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
dfflibmap(design, it.second);
cell_mappings.clear();