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Fixed type of sign extension in opt_const $eq/$ne handling
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ed4bcd52e5
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3 changed files with 26 additions and 9 deletions
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@ -151,8 +151,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
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int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
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a.extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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b.extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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a.extend_un0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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b.extend_un0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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}
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RTLIL::SigSpec new_a, new_b;
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@ -168,6 +168,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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new_b.append(b.chunks[i]);
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}
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if (new_a.width == 0) {
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RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0);
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new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
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replace_cell(module, cell, "empty", "\\Y", new_y);
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goto next_cell;
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}
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if (new_a.width != a.width) {
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new_a.optimize();
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new_b.optimize();
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@ -176,13 +183,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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cell->parameters["\\A_WIDTH"] = new_a.width;
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cell->parameters["\\B_WIDTH"] = new_b.width;
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}
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if (new_a.width == 0) {
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RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0);
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new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
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replace_cell(module, cell, "empty", "\\Y", new_y);
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goto next_cell;
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}
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}
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if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
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