1084 commits

Author	SHA1	Message	Date
Clifford Wolf	2733994aeb	Added clk2fflogic	2016-10-14 14:55:07 +02:00
Clifford Wolf	2ef454c3f5	Added opt_rmdff support for $ff cells	2016-10-14 13:02:36 +02:00
Clifford Wolf	53655d173b	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
Clifford Wolf	ffbb4e992e	Added MEMID handling to "flatten" pass	2016-10-14 10:36:37 +02:00
Clifford Wolf	ee91350add	Added "zinit" pass	2016-10-12 12:05:19 +02:00
Clifford Wolf	8ebba8a35f	Added $ff and $_FF_ cell types	2016-10-12 01:18:39 +02:00
Clifford Wolf	ed519f578e	Added "opt_rmdff -keepdc"	2016-09-30 17:02:38 +02:00
Clifford Wolf	e788ad4885	Cosmetic fix in test_autotb.cc	2016-09-19 20:43:43 +02:00
Clifford Wolf	5e155aa121	Avoid creating very long strings in test_autotb	2016-09-19 10:20:20 +02:00
Clifford Wolf	d8ad889594	Bugfix in techmap parameter handling	2016-09-14 20:46:54 +02:00
Kaj Tuomi	df4ab169a7	Typo fix.	2016-09-08 10:57:16 +03:00
Clifford Wolf	cb7dbf4070	Improvements in assertpmux	2016-09-07 12:42:16 +02:00
Clifford Wolf	ab18e9df7c	Added assertpmux	2016-09-07 00:28:01 +02:00
Clifford Wolf	f3f5a02045	Added "tee +INT -INT"	2016-09-06 17:43:24 +02:00
Clifford Wolf	fc5281b3f7	Run log_flush() before solving in sat command	2016-09-06 17:35:25 +02:00
Clifford Wolf	4ea7054b56	Improved init spec handling in opt_rmdff, modernized the code a bit	2016-08-30 01:34:04 +02:00
Clifford Wolf	eae390ae17	Removed $predict again	2016-08-28 21:35:33 +02:00
Clifford Wolf	66582964bc	Improved "show" help message	2016-08-28 12:34:36 +02:00
Clifford Wolf	23afeadb5e	Fixed handling of transparent bram rd ports on ROMs	2016-08-27 17:06:22 +02:00
Clifford Wolf	cad40fc874	Fixed bug in memory_share for memory ports with different ABITS	2016-08-22 14:26:33 +02:00
Clifford Wolf	d77a914683	Added "wreduce -memx"	2016-08-20 12:52:50 +02:00
Clifford Wolf	15ef608453	Added memory_memx pass, "memory -memx", and "prep -memx"	2016-08-19 19:48:26 +02:00
Clifford Wolf	f6629b9c29	Optimize memory address port width in wreduce and memory_collect, not verilog front-end	2016-08-19 18:38:25 +02:00
Clifford Wolf	b3a01451a5	Bugfix in test_autotb	2016-08-18 13:43:12 +02:00
Clifford Wolf	00f29d5e5c	Fixed use-after-free dict<> usage pattern in hierarchy.cc	2016-08-16 09:07:13 +02:00
Clifford Wolf	321e15b0bf	Minor fixes in show command	2016-08-16 00:36:24 +02:00
Clifford Wolf	73b7232ec8	Fixed some compiler warnings in attrmap command	2016-08-10 13:44:08 +02:00
Clifford Wolf	b0aab4e304	Added "attrmap" command	2016-08-09 19:56:55 +02:00
Clifford Wolf	3c6d31fd06	Added "attrmvcp" pass	2016-08-09 11:18:48 +02:00
Clifford Wolf	9d15529214	Undo "preserve wire attributes in iopadmap" change (it was OK before)	2016-08-08 11:47:35 +02:00
Clifford Wolf	88a67afa7d	Added "test_autotb -seed" (and "autotest.sh -S")	2016-08-06 13:32:29 +02:00
Clifford Wolf	90c17aad56	preserve wire attributes in iopadmap	2016-08-06 13:24:59 +02:00
Clifford Wolf	5d6765a9d2	Added "insbuf" command	2016-08-02 10:37:19 +02:00
Clifford Wolf	8537c4d206	Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()	2016-07-25 16:39:25 +02:00
Clifford Wolf	b1c432af56	Improvements in CellEdgesDatabase	2016-07-24 17:21:53 +02:00
Clifford Wolf	f162b858f2	Added CellEdgesDatabase API	2016-07-24 13:59:57 +02:00
Clifford Wolf	54966679df	Moved SatHelper::setup_init() code to SatHelper::setup()	2016-07-24 12:18:39 +02:00
Clifford Wolf	34e833103b	Added $initstate support to "sat" command	2016-07-23 17:01:03 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Clifford Wolf	e92998a79c	Minor bugfix in FSM reset state detection	2016-07-12 09:46:15 +02:00
Clifford Wolf	b5a9fba0db	Further improved fsm_detect output, attempt to detect self-resetting circuits	2016-07-09 14:02:49 +02:00
Clifford Wolf	d63ffabacb	Added printing of some warning messages to fsm_detect	2016-07-09 13:23:06 +02:00
Clifford Wolf	6ed6b3cb6d	Replaced "select -assert-limit" with -assert-max and -assert-min	2016-07-01 12:24:13 +02:00
eshellko	9a742f4069	Added 'assert-limit' option for 'select' command ... For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.	2016-07-01 10:24:22 +04:00
Clifford Wolf	541083cf32	Bugfix in "abc -script" handling	2016-06-19 22:19:19 +02:00
Clifford Wolf	ca91bccb6b	Added "deminout"	2016-06-19 13:08:16 +02:00
Clifford Wolf	3380281e15	Added "dc2" to default ABC scripts	2016-06-17 20:15:35 +02:00
Clifford Wolf	f498204ae4	Added "abc -I <num> -P <num>"	2016-06-17 19:39:35 +02:00
Clifford Wolf	95757efb25	Improved support for $sop cells	2016-06-17 16:31:16 +02:00