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Added $ff and $_FF_ cell types

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This commit is contained in:
Clifford Wolf 2016-10-12 01:18:39 +02:00
parent 4a981a3bd8
commit 8ebba8a35f
12 changed files with 118 additions and 19 deletions
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38
passes/sat/miter.cc
View file

@ -312,18 +312,42 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
log_pop();
}
SigSpec or_signals;
SigSpec assert_signals, assume_signals;
vector<Cell*> cell_list = module->cells();
for (auto cell : cell_list) {
for (auto cell : cell_list)
{
if (!cell->type.in("$assert", "$assume"))
continue;
SigBit is_active = module->Nex(NEW_ID, cell->getPort("\\A"), State::S1);
SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1);
if (cell->type == "$assert") {
SigBit is_active = module->Nex(NEW_ID, cell->getPort("\\A"), State::S1);
SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1);
or_signals.append(module->And(NEW_ID, is_active, is_enabled));
module->remove(cell);
assert_signals.append(module->And(NEW_ID, is_active, is_enabled));
} else {
assume_signals.append(module->And(NEW_ID, is_active, is_enabled));
}
module->remove(cell);
}
module->addReduceOr(NEW_ID, or_signals, trigger);
if (assume_signals.empty())
{
module->addReduceOr(NEW_ID, assert_signals, trigger);
}
else
{
Wire *assume_q = module->addWire(NEW_ID);
assume_q->attributes["\\init"] = State::S1;
assume_signals.append(assume_q);
SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals);
SigSpec assume_ok = module->Not(NEW_ID, assume_nok);
module->addFf(NEW_ID, assume_ok, assume_q);
SigSpec assert_fail = module->ReduceOr(NEW_ID, assert_signals);
module->addAnd(NEW_ID, assert_fail, assume_ok, trigger);
}
if (flag_flatten) {
log_push();

20
passes/techmap/simplemap.cc
View file

@ -388,6 +388,23 @@ void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at("\\WIDTH").as_int();
RTLIL::SigSpec sig_d = cell->getPort("\\D");
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
std::string gate_type = "$_FF_";
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
gate->setPort("\\D", sig_d[i]);
gate->setPort("\\Q", sig_q[i]);
}
}
void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at("\\WIDTH").as_int();
@ -532,6 +549,7 @@ void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTL
mappers["$slice"] = simplemap_slice;
mappers["$concat"] = simplemap_concat;
mappers["$sr"] = simplemap_sr;
mappers["$ff"] = simplemap_ff;
mappers["$dff"] = simplemap_dff;
mappers["$dffe"] = simplemap_dffe;
mappers["$dffsr"] = simplemap_dffsr;
@ -569,7 +587,7 @@ struct SimplemapPass : public Pass {
log(" $not, $pos, $and, $or, $xor, $xnor\n");
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
log(" $sr, $dff, $dffsr, $adff, $dlatch\n");
log(" $sr, $ff, $dff, $dffsr, $adff, $dlatch\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)