Miodrag Milanovic
144da16583
report on summary
2026-03-13 10:15:17 +01:00
Miodrag Milanovic
903c74e42b
Look for all result files
2026-03-13 10:10:34 +01:00
Miodrag Milanovic
f9cd49f7b9
Save results, and create summary and report
2026-03-13 09:51:15 +01:00
Miodrag Milanovic
2fb0ca49ff
Convert gen-tests shell script to python
2026-03-13 08:38:05 +01:00
Miodrag Milanovic
486c3715fb
Enabled realmath that was disabled for some reason
2026-03-11 08:02:11 +01:00
Miodrag Milanovic
2123121d23
Fix deprecation warning
2026-03-10 16:15:07 +01:00
Miodrag Milanovic
8a6954413f
Clean some seed-tests outputs
2026-03-10 15:57:24 +01:00
Miodrag Milanovic
ede782d7e3
Clean some seed-tests outputs
2026-03-10 11:50:30 +01:00
Miodrag Milanovic
a155994868
Cleanup for abcopt-tests
2026-03-10 11:18:05 +01:00
Miodrag Milanovic
169b9994dc
Ignore some generated files
2026-03-10 11:05:47 +01:00
Miodrag Milanovic
c08a2aa3ff
Do not write to console for makefile-tests
2026-03-10 11:02:20 +01:00
Miodrag Milanovic
1a864c72ae
Make sure targets are built for tests
2026-03-10 10:08:52 +01:00
Miodrag Milanovic
108a9133d0
Move clean for tests in proper Makefile
2026-03-10 10:01:23 +01:00
Miodrag Milanovic
92ef719434
Split vanilla-test to separate Makefile
2026-03-10 09:41:39 +01:00
abhinavputhran
314d01b35f
changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change
2026-03-08 20:14:03 -04:00
abhinavputhran
47c2257f82
setundef: more tests! and wire selection in -init mode
2026-03-08 19:41:31 -04:00
abhinavputhran
c23ba3f917
I think CI runs within the tests directory based on error so I changed the file path
2026-03-08 18:15:35 -04:00
abhinavputhran
5048dac854
setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer
2026-03-06 18:12:03 -05:00
Lofty
050483a6b2
Merge pull request #5698 from YosysHQ/lofty/analogdevices
...
synth_analogdevices: synthesis for Analog Devices EFLX FPGAs [sc-273]
2026-03-06 08:57:59 +00:00
Miodrag Milanovic
602f3fd1a5
Add missing EOL
2026-03-06 09:10:55 +01:00
Miodrag Milanovic
52533b0d1c
Update opt_lut_ins and stat for analogdevices and remove ecp5
2026-03-06 09:10:36 +01:00
Robert O'Callahan
1260fda83a
Add 'init' attributes to RTLIL fuzzing
2026-03-06 02:20:08 +00:00
Robert O'Callahan
cdfc586f18
Add unit tests for ConcurrentWorkQueue
2026-03-06 02:20:08 +00:00
Robert O'Callahan
1e96328ede
Add some tests for ShardedHashSet
2026-03-06 02:20:08 +00:00
Robert O'Callahan
3910d569da
Add unit tests for ConcurrentQueue and ThreadPool
2026-03-06 02:20:08 +00:00
Robert O'Callahan
ac55935a68
Add unit-tests for ParallelDispatchThread and friends
2026-03-06 02:20:08 +00:00
Robert O'Callahan
7f3b11e56b
Add test that connects a wire with init to a constant
2026-03-06 02:20:08 +00:00
Justin Zaun
9288889e20
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
...
Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
2026-03-05 16:04:23 +01:00
Emil J
629bf3dffd
Merge pull request #5630 from apullin/array-assignment
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ast: Add support for array-to-array assignment
2026-03-05 11:10:12 +00:00
Lofty
cd60dd4912
synth_analogdevices: update timing model and tests
2026-03-05 05:37:13 +00:00
Krystine Sherwin
5d3ed5a418
analogdevices: Extra tests
...
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
2026-03-05 05:37:13 +00:00
Lofty
39cb61615f
analogdevices: DSP inference
2026-03-05 05:37:12 +00:00
Krystine Sherwin
9be3cfb3f9
analogdevices: Update lutram.ys test
2026-03-05 05:37:12 +00:00
Lofty
6f205b41f5
test suite
2026-03-05 05:37:12 +00:00
Andrew Pullin
6ac8c8cb05
ast: Add support for array-to-array assignment
...
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:
1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`
Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.
Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
2026-03-04 21:34:40 -08:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes
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celltypes: compile-time lookup tables for internal cells
2026-03-04 14:47:57 +00:00
nella
b8ee0803ab
Remove todo.
2026-03-04 12:39:45 +01:00
nella
66bd4716cf
rtlil use newcelltypes.
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
6d4736269b
newcelltypes: extend testing
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ae10e9e955
pyosys: disable test
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
f594014bef
newcelltypes: proper bounds for unit test
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
d91e1c8607
newcelltypes: test against builtin_ff_cell_types
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
2d7d6ca10b
newcelltypes: unit test
2026-03-04 12:22:14 +01:00
Miodrag Milanović
05d1d56b9d
Merge pull request #5704 from apullin/apullin/abc9-no-loops-fix
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abc9: preserve topological-loop asserts with targeted SCC fallback
2026-03-04 11:09:38 +01:00
Emil J. Tywoniak
5b4603c54f
dfflibmap: fix formal $dffsr tests with sat, prove "no s&r" assumption only needed when appropriate
2026-03-03 10:35:03 +01:00
Emil J. Tywoniak
024408004a
dfflibmap: allow formal dffsr mapping tests with clk2fflogic
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
2dddc53ccf
dfflibmap: test dffsr and dffsre from proc with equiv
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
c13a623dbc
dfflibmap: test dffsr with either priority liberty file
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
ffb76a3486
dfflibmap: test dffsr mapping without assume
2026-03-03 10:34:29 +01:00
likeamahoney
e9442194f2
support automatic lifetime qualifier on procedural variables
2026-02-27 20:42:52 +03:00
