1571 commits

Author	SHA1	Message	Date
Eddie Hung	9fd2ddb14c	Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 ... Rename abc_* names/attributes to more precisely be abc9_*	2019-10-08 10:53:38 -07:00
Eddie Hung	4f0818275f	Cleanup	2019-10-07 15:58:55 -07:00
Eddie Hung	b2e34f932a	Rename $currQ to $abc9_currQ	2019-10-07 15:31:43 -07:00
Eddie Hung	bae3d8705d	Update comments in abc9_map.v	2019-10-07 12:54:45 -07:00
Eddie Hung	1dc22607c3	Remove -D_ABC9	2019-10-07 12:21:52 -07:00
Eddie Hung	3879ca1398	Do not require changes to cells_sim.v; try and work out comb model	2019-10-05 22:55:18 -07:00
Eddie Hung	6c5e1234e1	Add comment on why partial multipliers are 18x18	2019-10-04 22:31:04 -07:00
Eddie Hung	b47bb5c810	Fix typo in check_label()	2019-10-04 21:43:50 -07:00
Eddie Hung	a2ef93f03a	abc -> abc9	2019-10-04 17:56:38 -07:00
Eddie Hung	a5ac33f230	Merge branch 'master' into eddie/abc_to_abc9	2019-10-04 17:53:20 -07:00
Eddie Hung	bbc0e06af3	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-10-04 17:39:08 -07:00
Eddie Hung	0acc51c3d8	Add temporary abc9 -nomfs and use for synth_xilinx -abc9	2019-10-04 17:35:43 -07:00
Eddie Hung	d4212d128b	Use read_args for read_verilog	2019-10-04 17:27:05 -07:00
Eddie Hung	9c23811839	Remove DSP48E1 from *_cells_xtra.v	2019-10-04 17:26:42 -07:00
Eddie Hung	7959e9d6b2	Fix merge issues	2019-10-04 17:21:14 -07:00
Eddie Hung	7a45cd5856	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	2019-10-04 16:58:55 -07:00
Eddie Hung	aae2b9fd9c	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
Eddie Hung	9fef1df3c1	Panic over. Model was elsewhere. Re-arrange for consistency	2019-10-04 10:48:44 -07:00
Eddie Hung	4e11782cde	Oops	2019-10-04 10:36:02 -07:00
Eddie Hung	c0f54d3fd5	Ohmilord this wasn't added all this time!?!	2019-10-04 10:34:16 -07:00
Miodrag Milanovic	44c3472b9f	FF should be initialized to 0	2019-10-04 13:27:10 +02:00
Miodrag Milanovic	77d557d00b	Add missing latch mapping	2019-10-04 12:58:11 +02:00
Eddie Hung	549d6ea467	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-10-03 10:55:23 -07:00
Eddie Hung	655f1b2ac5	English	2019-10-03 10:11:25 -07:00
Eddie Hung	5299884f04	More fixes	2019-10-01 13:41:08 -07:00
Eddie Hung	03ebe43e3e	Escape Verilog identifiers for legality outside of Yosys	2019-10-01 13:05:56 -07:00
David Shah	b424d374db	ecp5: Fix shuffle_enable port ... Signed-off-by: David Shah <dave@ds0.me>	2019-10-01 14:14:46 +01:00
David Shah	7a1538cd36	ecp5: Add support for mapping 36-bit wide PDP BRAMs ... Signed-off-by: David Shah <dave@ds0.me>	2019-10-01 13:46:36 +01:00
Eddie Hung	e529872b01	Remove need for $currQ port connection	2019-09-30 16:33:40 -07:00
Eddie Hung	5e9ae90cbb	Add explanation to abc_map.v	2019-09-30 15:39:24 -07:00
Eddie Hung	8684b58bed	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-30 12:29:35 -07:00
Eddie Hung	5b5756b91e	Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}	2019-09-30 12:52:43 +02:00
Marcin Kościelnicki	4535f2c694	synth_xilinx: Support latches, remove used-up FF init values. ... Fixes #1387.	2019-09-30 12:52:43 +02:00
Eddie Hung	f6203e6bd6	Missing endmodule	2019-09-29 21:55:53 -07:00
Eddie Hung	1123c09588	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-29 19:39:12 -07:00
Eddie Hung	8474c5b366	Merge pull request #1359 from YosysHQ/xc7dsp ... DSP inference for Xilinx (improved for ice40, initial support for ecp5)	2019-09-29 11:26:22 -07:00
Eddie Hung	18ebb86edb	FDCE_1 does not have IS_CLR_INVERTED	2019-09-29 11:25:34 -07:00
Eddie Hung	f3e150d9a5	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-29 09:21:51 -07:00
Eddie Hung	79b6edb639	Big rework; flop info now mostly in cells_sim.v	2019-09-28 23:48:17 -07:00
Eddie Hung	c372e7baf9	Fix box name	2019-09-27 18:49:45 -07:00
Eddie Hung	8f5710c464	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-27 15:14:31 -07:00
Eddie Hung	b3d8a60cbd	Re-order	2019-09-27 14:32:07 -07:00
Eddie Hung	90236025b7	Missing (* mul2dsp *) for sliceB	2019-09-27 14:21:47 -07:00
Eddie Hung	143f82def2	Missing an '&'	2019-09-26 11:13:08 -07:00
Eddie Hung	84825f9378	Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once	2019-09-26 10:45:14 -07:00
Eddie Hung	033aefc0f4	Typo	2019-09-26 10:34:14 -07:00
Eddie Hung	781dda6175	select once	2019-09-26 10:15:05 -07:00
Eddie Hung	27e5bf5aad	Stop trying to be too smart by prematurely optimising	2019-09-26 09:57:11 -07:00
Eddie Hung	35aaa8d73a	mul2dsp.v slice names	2019-09-25 22:58:55 -07:00
Eddie Hung	34aa3532fb	Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit	2019-09-25 17:26:47 -07:00