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https://github.com/YosysHQ/yosys
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Do not require changes to cells_sim.v; try and work out comb model
This commit is contained in:
Eddie Hung
parent
3c6e5d82a6
commit
3879ca1398
6 changed files with 277 additions and 309 deletions
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@ -49,8 +49,57 @@ module FDRE (output reg Q, input C, CE, D, R);
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
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);
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wire _TECHMAP_REPLACE_.$currQ = Q;
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// `abc9' requires that complex flops be split into a combinatorial box
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// feeding a simple flop ($_ABC9_FF_).
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// Yosys will automatically analyse the simulation model (described in
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// cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
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// order to extract the combinatorial control logic left behind.
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// Specifically, a simulation model similar to the one below:
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//
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// ++===================================++
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// || Sim model ||
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// || /\/\/\/\ ||
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// D -->>-----< > +------+ ||
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// R -->>-----< Comb. > |$_DFF_| ||
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// CE -->>-----< logic >-----| [NP]_|---+---->>-- Q
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// || +--< > +------+ | ||
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// || | \/\/\/\/ | ||
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// || | | ||
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// || +----------------------------+ ||
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// || ||
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// ++===================================++
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//
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// is transformed into:
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//
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// ++==================++
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// || Comb box ||
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// || ||
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// || /\/\/\/\ ||
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// D -->>-----< > || +------+
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// R -->>-----< Comb. > || |$_ABC_|
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// CE -->>-----< logic >--->>-- $nextQ --| FF_ |--+-->> Q
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// $currQ +-->>-----< > || +------+ |
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// | || \/\/\/\/ || |
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// | || || |
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// | ++==================++ |
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// | |
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// +----------------------------------------------+
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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// Special signal indicating control domain
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// (which, combined with this cell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
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// Special signal indicating the current value of the flip-flop
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `$currQ' wire.
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wire _TECHMAP_REPLACE_.$currQ = Q;
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endmodule
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module FDRE_1 (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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@ -60,8 +109,22 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
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);
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wire _TECHMAP_REPLACE_.$currQ = Q;
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
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// Special signal indicating the current value of the flip-flop
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `$currQ' wire.
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wire _TECHMAP_REPLACE_.$currQ = Q;
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endmodule
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module FDCE (output reg Q, input C, CE, D, CLR);
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@ -69,18 +132,38 @@ module FDCE (output reg Q, input C, CE, D, CLR);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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wire $currQ, $nextQ;
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wire $nextQ, $currQ;
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FDCE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_CLR_INVERTED(IS_CLR_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
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.D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(IS_CLR_INVERTED)
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// ^^^ Note that async
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// control is disabled
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// and captured by
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// $__ABC9_ASYNC below
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);
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wire _TECHMAP_REPLACE_.$currQ = Q;
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
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\$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
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// Since this is an async flop, async behaviour is also dealt with
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// using the $_ABC9_ASYNC box by abc9_map.v
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\$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
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// Special signal indicating the current value of the flip-flop
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `$currQ' wire.
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wire _TECHMAP_REPLACE_.$currQ = $currQ;
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endmodule
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module FDCE_1 (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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@ -88,11 +171,29 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
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FDCE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
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.D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(1'b0)
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// ^^^ Note that async
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// control is disabled
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// and captured by
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// $__ABC9_ASYNC below
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);
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wire _TECHMAP_REPLACE_.$currQ = Q;
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
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\$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
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\$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
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// Special signal indicating the current value of the flip-flop
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `$currQ' wire.
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wire _TECHMAP_REPLACE_.$currQ = $currQ;
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endmodule
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module FDPE (output reg Q, input C, CE, D, PRE);
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@ -107,11 +208,29 @@ module FDPE (output reg Q, input C, CE, D, PRE);
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_PRE_INVERTED(IS_PRE_INVERTED),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
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.D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(IS_PRE_INVERTED)
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// ^^^ Note that async
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// control is disabled
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// and captured by
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// $__ABC9_ASYNC below
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);
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wire _TECHMAP_REPLACE_.$currQ = Q;
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
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\$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
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\$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
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// Special signal indicating the current value of the flip-flop
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `$currQ' wire.
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wire _TECHMAP_REPLACE_.$currQ = $currQ;
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endmodule
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module FDPE_1 (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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@ -119,11 +238,29 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
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FDPE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
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.D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(1'b0)
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// ^^^ Note that async
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// control is disabled
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// and captured by
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// $__ABC9_ASYNC below
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);
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wire _TECHMAP_REPLACE_.$currQ = Q;
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
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\$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
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\$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
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// Special signal indicating the current value of the flip-flop
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `$currQ' wire.
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wire _TECHMAP_REPLACE_.$currQ = $currQ;
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endmodule
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module FDSE (output reg Q, input C, CE, D, S);
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@ -140,8 +277,22 @@ module FDSE (output reg Q, input C, CE, D, S);
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
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);
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wire _TECHMAP_REPLACE_.$currQ = Q;
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
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// Special signal indicating the current value of the flip-flop
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `$currQ' wire.
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wire _TECHMAP_REPLACE_.$currQ = Q;
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endmodule
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module FDSE_1 (output reg Q, input C, CE, D, S);
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parameter [0:0] INIT = 1'b0;
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@ -151,8 +302,22 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
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);
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wire _TECHMAP_REPLACE_.$currQ = Q;
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
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// Special signal indicating the current value of the flip-flop
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `$currQ' wire.
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wire _TECHMAP_REPLACE_.$currQ = Q;
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endmodule
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module RAM32X1D (
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@ -30,11 +30,8 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
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: (S0 ? I1 : I0);
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endmodule
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module \$__ABC_FF_ (input D, output Q);
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endmodule
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(* abc_box_id = 1000 *)
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module \$__ABC_ASYNC (input A, S, output Y);
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module \$__ABC9_ASYNC (input A, S, output Y);
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endmodule
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// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
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@ -44,7 +44,7 @@ CARRY4 4 1 10 8
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# Box to emulate async behaviour of FD[CP]*
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# Inputs: A S
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# Outputs: Y
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$__ABC_ASYNC 1000 0 2 1
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$__ABC9_ASYNC 1000 0 2 1
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0 764
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# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
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@ -258,33 +258,10 @@ module FDRE (
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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initial Q <= INIT;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
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`ifdef _ABC9
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `$currQ' wire.
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
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always @* Q = \$nextQ ;
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`else
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assign \$currQ = Q;
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generate case (|IS_C_INVERTED)
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1'b0: always @(posedge C) Q <= \$nextQ ;
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1'b1: always @(negedge C) Q <= \$nextQ ;
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1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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endcase endgenerate
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`endif
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endmodule
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(* abc9_box_id=1002, lib_whitebox, abc9_flop *)
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@ -297,30 +274,7 @@ module FDRE_1 (
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
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`ifdef _ABC9
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `$currQ' wire.
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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// Special signal indicating control domain
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||||
// (which, combined with this spell type, encodes to `abc9'
|
||||
// which flops may be merged together)
|
||||
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
|
||||
always @* Q = \$nextQ ;
|
||||
`else
|
||||
assign \$currQ = Q;
|
||||
always @(negedge C) Q <= \$nextQ ;
|
||||
`endif
|
||||
always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1003, lib_whitebox, abc9_flop *)
|
||||
|
|
@ -341,37 +295,12 @@ module FDCE (
|
|||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_CLR_INVERTED = 1'b0;
|
||||
initial Q <= INIT;
|
||||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
// Since this is an async flop, async behaviour is also dealt with
|
||||
// using the $_ABC9_ASYNC box by abc9_map.v
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
// sequential synthesis (reachability analysis) correctly on
|
||||
// one domain at a time)
|
||||
wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
|
||||
// Special signal indicating control domain
|
||||
// (which, combined with this spell type, encodes to `abc9'
|
||||
// which flops may be merged together)
|
||||
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
|
||||
always @* Q = \$nextQ ;
|
||||
`else
|
||||
assign \$currQ = Q;
|
||||
generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
|
||||
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
|
||||
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
|
||||
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
|
||||
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
|
||||
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
endcase endgenerate
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1004, lib_whitebox, abc9_flop *)
|
||||
|
|
@ -384,32 +313,7 @@ module FDCE_1 (
|
|||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
// Since this is an async flop, async behaviour is also dealt with
|
||||
// using the $_ABC9_ASYNC box by abc9_map.v
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
// sequential synthesis (reachability analysis) correctly on
|
||||
// one domain at a time)
|
||||
wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
|
||||
// Special signal indicating control domain
|
||||
// (which, combined with this spell type, encodes to `abc9'
|
||||
// which flops may be merged together)
|
||||
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
|
||||
always @* Q = \$nextQ ;
|
||||
`else
|
||||
assign \$currQ = Q;
|
||||
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
|
||||
`endif
|
||||
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1005, lib_whitebox, abc9_flop *)
|
||||
|
|
@ -430,37 +334,12 @@ module FDPE (
|
|||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_PRE_INVERTED = 1'b0;
|
||||
initial Q <= INIT;
|
||||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
// Since this is an async flop, async behaviour is also dealt with
|
||||
// using the $_ABC9_ASYNC box by abc9_map.v
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
// sequential synthesis (reachability analysis) correctly on
|
||||
// one domain at a time)
|
||||
wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
|
||||
// Special signal indicating control domain
|
||||
// (which, combined with this spell type, encodes to `abc9'
|
||||
// which flops may be merged together)
|
||||
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
|
||||
always @* Q = \$nextQ ;
|
||||
`else
|
||||
assign \$currQ = Q;
|
||||
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
|
||||
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
|
||||
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
|
||||
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
|
||||
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
|
||||
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
|
||||
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
|
||||
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
|
||||
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
|
||||
endcase endgenerate
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1006, lib_whitebox, abc9_flop *)
|
||||
|
|
@ -473,32 +352,7 @@ module FDPE_1 (
|
|||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
// Since this is an async flop, async behaviour is also dealt with
|
||||
// using the $_ABC9_ASYNC box by abc9_map.v
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
// sequential synthesis (reachability analysis) correctly on
|
||||
// one domain at a time)
|
||||
wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
|
||||
// Special signal indicating control domain
|
||||
// (which, combined with this spell type, encodes to `abc9'
|
||||
// which flops may be merged together)
|
||||
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
|
||||
always @* Q = \$nextQ ;
|
||||
`else
|
||||
assign \$currQ = Q;
|
||||
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
|
||||
`endif
|
||||
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1007, lib_whitebox, abc9_flop *)
|
||||
|
|
@ -519,33 +373,10 @@ module FDSE (
|
|||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_S_INVERTED = 1'b0;
|
||||
initial Q <= INIT;
|
||||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
// sequential synthesis (reachability analysis) correctly on
|
||||
// one domain at a time)
|
||||
wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
|
||||
// Special signal indicating control domain
|
||||
// (which, combined with this spell type, encodes to `abc9'
|
||||
// which flops may be merged together)
|
||||
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
|
||||
always @* Q = \$nextQ ;
|
||||
`else
|
||||
assign \$currQ = Q;
|
||||
generate case (|IS_C_INVERTED)
|
||||
1'b0: always @(posedge C) Q <= \$nextQ ;
|
||||
1'b1: always @(negedge C) Q <= \$nextQ ;
|
||||
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
|
||||
endcase endgenerate
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
(* abc9_box_id=1008, lib_whitebox, abc9_flop *)
|
||||
|
|
@ -558,30 +389,7 @@ module FDSE_1 (
|
|||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
wire \$currQ ;
|
||||
reg \$nextQ ;
|
||||
always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
|
||||
`ifdef _ABC9
|
||||
// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `$currQ' wire.
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
// sequential synthesis (reachability analysis) correctly on
|
||||
// one domain at a time)
|
||||
wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
|
||||
// Special signal indicating control domain
|
||||
// (which, combined with this spell type, encodes to `abc9'
|
||||
// which flops may be merged together)
|
||||
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
|
||||
always @* Q = \$nextQ ;
|
||||
`else
|
||||
assign \$currQ = Q;
|
||||
always @(negedge C) Q <= \$nextQ ;
|
||||
`endif
|
||||
always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module LDCE (
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue