Eddie Hung 03ebe43e3e Escape Verilog identifiers for legality outside of Yosys		2019-10-01 13:05:56 -07:00
..
achronix	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
anlogic	make note that it is for latch mode	2019-09-18 17:48:16 +02:00
common	Missing (* mul2dsp *) for sliceB	2019-09-27 14:21:47 -07:00
coolrunner2	Fix spacing	2019-08-06 16:47:55 -07:00
easic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ecp5	Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once	2019-09-26 10:45:14 -07:00
efinix	better handling of lut and begin/end add	2019-09-18 17:45:07 +02:00
gowin	Fix formatting for msys2 mingw build using GetSize	2019-08-01 17:27:34 +02:00
greenpak4	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ice40	Re-order	2019-09-27 14:32:07 -07:00
intel	techlibs/intel: Clean up Makefile	2019-08-05 11:22:11 -07:00
sf2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
xilinx	Escape Verilog identifiers for legality outside of Yosys	2019-10-01 13:05:56 -07:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00