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Escape Verilog identifiers for legality outside of Yosys
This commit is contained in:
Eddie Hung
parent
1b96d29174
commit
03ebe43e3e
1 changed files with 48 additions and 48 deletions
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@ -258,9 +258,9 @@ module FDRE (
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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initial Q <= INIT;
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wire $currQ;
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reg $nextQ;
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always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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@ -277,12 +277,12 @@ module FDRE (
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
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always @* Q = $nextQ;
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always @* Q = \$nextQ ;
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`else
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assign $currQ = Q;
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generate case (|IS_C_INVERTED)
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1'b0: always @(posedge C) Q <= $nextQ;
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1'b1: always @(negedge C) Q <= $nextQ;
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1'b0: always @(posedge C) Q <= \$nextQ ;
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1'b1: always @(negedge C) Q <= \$nextQ ;
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endcase endgenerate
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`endif
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endmodule
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@ -297,9 +297,9 @@ module FDRE_1 (
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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wire $currQ;
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reg $nextQ;
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always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = $currQ;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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@ -316,10 +316,10 @@ module FDRE_1 (
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
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always @* Q = $nextQ;
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always @* Q = \$nextQ ;
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`else
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assign $currQ = Q;
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always @(negedge C) Q <= $nextQ;
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always @(negedge C) Q <= \$nextQ ;
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`endif
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endmodule
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@ -341,9 +341,9 @@ module FDCE (
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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initial Q <= INIT;
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wire $currQ;
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reg $nextQ;
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always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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@ -362,14 +362,14 @@ module FDCE (
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
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always @* Q = $nextQ;
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always @* Q = \$nextQ ;
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`else
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assign $currQ = Q;
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generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
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2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ;
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2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ;
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2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ;
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2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ;
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2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
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2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
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2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
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2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
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endcase endgenerate
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`endif
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endmodule
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@ -384,9 +384,9 @@ module FDCE_1 (
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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wire $currQ;
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reg $nextQ;
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always @* if (CE) Q <= D; else $nextQ = $currQ;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (CE) Q <= D; else $nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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@ -405,10 +405,10 @@ module FDCE_1 (
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
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always @* Q = $nextQ;
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always @* Q = \$nextQ ;
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`else
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assign $currQ = Q;
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always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= $nextQ;
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always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
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`endif
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endmodule
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@ -430,9 +430,9 @@ module FDPE (
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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initial Q <= INIT;
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wire $currQ;
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reg $nextQ;
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always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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@ -451,14 +451,14 @@ module FDPE (
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
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always @* Q = $nextQ;
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always @* Q = \$nextQ ;
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`else
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assign $currQ = Q;
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generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
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2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ;
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2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ;
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2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ;
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2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ;
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2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
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2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
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2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
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2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
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endcase endgenerate
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`endif
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endmodule
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@ -473,9 +473,9 @@ module FDPE_1 (
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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wire $currQ;
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reg $nextQ;
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always @* if (CE) Q <= D; else $nextQ = $currQ;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (CE) Q <= D; else $nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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@ -494,10 +494,10 @@ module FDPE_1 (
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
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always @* Q = $nextQ;
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always @* Q = \$nextQ ;
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`else
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assign $currQ = Q;
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always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= $nextQ;
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always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
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`endif
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endmodule
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@ -519,9 +519,9 @@ module FDSE (
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_S_INVERTED = 1'b0;
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initial Q <= INIT;
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wire $currQ;
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reg $nextQ;
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always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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@ -538,12 +538,12 @@ module FDSE (
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
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always @* Q = $nextQ;
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always @* Q = \$nextQ ;
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`else
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assign $currQ = Q;
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generate case (|IS_C_INVERTED)
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1'b0: always @(posedge C) Q <= $nextQ;
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1'b1: always @(negedge C) Q <= $nextQ;
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1'b0: always @(posedge C) Q <= \$nextQ ;
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1'b1: always @(negedge C) Q <= \$nextQ ;
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endcase endgenerate
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`endif
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endmodule
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@ -558,9 +558,9 @@ module FDSE_1 (
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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wire $currQ;
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reg $nextQ;
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always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = $currQ;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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@ -577,10 +577,10 @@ module FDSE_1 (
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
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always @* Q = $nextQ;
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always @* Q = \$nextQ ;
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`else
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assign $currQ = Q;
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always @(negedge C) Q <= $nextQ;
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always @(negedge C) Q <= \$nextQ ;
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`endif
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endmodule
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