mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-30 12:25:52 +00:00
Code Activity

English

Browse source
This commit is contained in:
Eddie Hung 2019-10-03 10:11:25 -07:00
parent 5299884f04
commit 655f1b2ac5
1 changed files with 3 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/xilinx/abc_map.v
View file

@ -29,11 +29,11 @@
// ============================================================================
// The purpose of the following FD* rules are to wrap the flop (which, when
// called with the `_ABC' macro set captures contains only its combinatorial
// called with the `_ABC' macro set captures only its combinatorial
// behaviour) with:
// (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9
// the location of its basic D-Q flop
// (b) a special TECHMAP_REPLACE_.$currQwire that will be used for feedback
// the connectivity of its basic D-Q flop
// (b) a special TECHMAP_REPLACE_.$currQ wire that will be used for feedback
// into the (combinatorial) FD* cell to facilitate clock-enable behaviour
module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;