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Big rework; flop info now mostly in cells_sim.v

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This commit is contained in:
Eddie Hung 2019-09-28 23:48:17 -07:00
parent cfa6dd61ef
commit 79b6edb639
9 changed files with 500 additions and 456 deletions
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77
techlibs/xilinx/abc_map.v
View file

@ -26,27 +26,23 @@ module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
wire \$nextQ ;
\$__ABC_FDRE #(
FDRE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_R_INVERTED(IS_R_INVERTED),
.CLK_POLARITY(!IS_C_INVERTED),
.EN_POLARITY(1'b1)
.IS_R_INVERTED(IS_R_INVERTED)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
.D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
endmodule
module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
wire \$nextQ ;
\$__ABC_FDRE_1 #(
.INIT(|0),
.CLK_POLARITY(1'b0),
.EN_POLARITY(1'b1)
FDRE_1 #(
.INIT(|0),
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
.D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
endmodule
@ -57,28 +53,24 @@ module FDCE (output reg Q, input C, CE, D, CLR);
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDCE #(
FDCE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_CLR_INVERTED(IS_CLR_INVERTED),
.CLK_POLARITY(!IS_C_INVERTED),
.EN_POLARITY(1'b1)
.IS_CLR_INVERTED(IS_CLR_INVERTED)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
.D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
endmodule
module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDCE_1 #(
.INIT(INIT),
.CLK_POLARITY(1'b0),
.EN_POLARITY(1'b1)
FDCE_1 #(
.INIT(INIT)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
.D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
@ -90,33 +82,56 @@ module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDPE #(
FDPE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_PRE_INVERTED(IS_PRE_INVERTED),
.CLK_POLARITY(!IS_C_INVERTED),
.EN_POLARITY(1'b1)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
.D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
endmodule
module FDPE_1 (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDPE_1 #(
.INIT(INIT),
.CLK_POLARITY(1'b0),
.EN_POLARITY(1'b1)
FDPE_1 #(
.INIT(INIT)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
.D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
endmodule
module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
wire \$nextQ ;
FDSE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_S_INVERTED(IS_S_INVERTED)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
endmodule
module FDSE_1 (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b0;
wire \$nextQ ;
FDSE_1 #(
.INIT(|0),
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
endmodule
module RAM32X1D (
output DPO, SPO,
input D,

90
techlibs/xilinx/abc_model.v
View file

@ -26,97 +26,9 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
: (S0 ? I1 : I0);
endmodule
module \$__ABC_FF_ (input C, D, output Q);
module \$__ABC_FF_ (input D, output Q);
endmodule
(* abc_box_id = 1000 *)
module \$__ABC_ASYNC (input A, S, output Y);
endmodule
(* abc_box_id=1001, lib_whitebox, abc_flop *)
module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
endmodule
(* abc_box_id=1002, lib_whitebox, abc_flop *)
module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
endmodule
(* abc_box_id=1003, lib_whitebox, abc_flop *)
module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule
(* abc_box_id=1004, lib_whitebox, abc_flop *)
module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
assign Q = (CE && !CLR) ? D : \$pastQ ;
endmodule
(* abc_box_id=1005, lib_whitebox, abc_flop *)
module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule
(* abc_box_id=1006, lib_whitebox, abc_flop *)
module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
assign Q = (CE && !PRE) ? D : \$pastQ ;
endmodule
(* abc_box_id=2000 *)
module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
endmodule
(* abc_box_id=2001 *)
module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
endmodule

122
techlibs/xilinx/abc_unmap.v
View file

@ -24,124 +24,6 @@ module \$__ABC_ASYNC (input A, S, output Y);
assign Y = A;
endmodule
module \$__ABC_FDRE (output Q,
input C,
input CE,
input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
FDRE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_R_INVERTED(IS_R_INVERTED),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
);
endmodule
module \$__ABC_FDRE_1 (output Q,
input C,
input CE,
input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
FDRE_1 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
);
endmodule
module \$__ABC_FDCE (output Q,
input C,
input CE,
input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
FDCE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_CLR_INVERTED(IS_CLR_INVERTED),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
);
endmodule
module \$__ABC_FDCE_1 (output Q,
input C,
input CE,
input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
FDCE_1 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
);
endmodule
module \$__ABC_FDPE (output Q,
input C,
input CE,
input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
FDPE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_PRE_INVERTED(IS_PRE_INVERTED),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
);
endmodule
module \$__ABC_FDPE_1 (output Q,
input C,
input CE,
input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
FDPE_1 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
);
endmodule
module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
assign Y = A;
endmodule
module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
assign Y = A;
module \$__ABC_FF_ (input D, output Q);
assign Q = D;
endmodule

22
techlibs/xilinx/abc_xc7.box
View file

@ -52,36 +52,46 @@ $__ABC_ASYNC 1000 0 2 1
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
# Inputs: C CE D R \$pastQ
# Inputs: C CE D R \$currQ
# Outputs: Q
FDRE 1001 1 5 1
0 151 0 446 0
# Inputs: C CE D R \$pastQ
# Inputs: C CE D R \$currQ
# Outputs: Q
FDRE_1 1002 1 5 1
0 151 0 446 0
# Inputs: C CE CLR D \$pastQ
# Inputs: C CE CLR D \$currQ
# Outputs: Q
FDCE 1003 1 5 1
0 151 806 0 0
# Inputs: C CE CLR D \$pastQ
# Inputs: C CE CLR D \$currQ
# Outputs: Q
FDCE_1 1004 1 5 1
0 151 806 0 0
# Inputs: C CE D PRE \$pastQ
# Inputs: C CE D PRE \$currQ
# Outputs: Q
FDPE 1005 1 5 1
0 151 0 806 0
# Inputs: C CE D PRE \$pastQ
# Inputs: C CE D PRE \$currQ
# Outputs: Q
FDPE_1 1006 1 5 1
0 151 0 806 0
# Inputs: C CE D S \$currQ
# Outputs: Q
FDSE 1007 1 5 1
0 151 0 446 0
# Inputs: C CE D S \$currQ
# Outputs: Q
FDSE_1 1008 1 5 1
0 151 0 446 0
# SLICEM/A6LUT
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
# Necessary since RAMD* and SRL* have both combinatorial (i.e.

324
techlibs/xilinx/cells_sim.v
View file

@ -240,6 +240,7 @@ endmodule
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
(* abc_box_id=1001, lib_whitebox, abc9_flop *)
module FDRE (
(* abc_arrival=303 *)
output reg Q,
@ -257,35 +258,72 @@ module FDRE (
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
`ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `\$currQ' wire.
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b0: always @(posedge C) Q <= \$nextQ ;
1'b1: always @(negedge C) Q <= \$nextQ ;
endcase endgenerate
`endif
endmodule
module FDSE (
(* abc_box_id=1002, lib_whitebox, abc9_flop *)
module FDRE_1 (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
(* invertible_pin = "IS_D_INVERTED" *)
input D,
(* invertible_pin = "IS_S_INVERTED" *)
input S
input CE, D, R
);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
wire \$currQ ;
reg \$nextQ ;
always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
`ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `\$currQ' wire.
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
always @(negedge C) Q <= \$nextQ ;
`endif
endmodule
(* abc_box_id=1003, lib_whitebox, abc9_flop *)
module FDCE (
(* abc_arrival=303 *)
output reg Q,
@ -303,14 +341,78 @@ module FDCE (
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
`ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `\$currQ' wire.
// Since this is an async flop, async behaviour is also dealt with
// using the $_ABC_ASYNC box by abc_map.v
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
endcase endgenerate
`endif
endmodule
(* abc_box_id=1004, lib_whitebox, abc9_flop *)
module FDCE_1 (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
input CE, D, CLR
);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
`ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `\$currQ' wire.
// Since this is an async flop, async behaviour is also dealt with
// using the $_ABC_ASYNC box by abc_map.v
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ;
`endif
endmodule
(* abc_box_id=1005, lib_whitebox, abc9_flop *)
module FDPE (
(* abc_arrival=303 *)
output reg Q,
@ -328,50 +430,40 @@ module FDPE (
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
`ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `\$currQ' wire.
// Since this is an async flop, async behaviour is also dealt with
// using the $_ABC_ASYNC box by abc_map.v
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
endcase endgenerate
`endif
endmodule
module FDRE_1 (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
input CE, D, R
);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule
module FDSE_1 (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
input CE, D, S
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule
module FDCE_1 (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
input CE, D, CLR
);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
(* abc_box_id=1006, lib_whitebox, abc9_flop *)
module FDPE_1 (
(* abc_arrival=303 *)
output reg Q,
@ -381,7 +473,115 @@ module FDPE_1 (
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
wire \$currQ ;
reg \$nextQ ;
always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
`ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `\$currQ' wire.
// Since this is an async flop, async behaviour is also dealt with
// using the $_ABC_ASYNC box by abc_map.v
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
`endif
endmodule
(* abc_box_id=1007, lib_whitebox, abc9_flop *)
module FDSE (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
(* invertible_pin = "IS_D_INVERTED" *)
input D,
(* invertible_pin = "IS_S_INVERTED" *)
input S
);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
`ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `\$currQ' wire.
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) Q <= \$nextQ ;
1'b1: always @(negedge C) Q <= \$nextQ ;
endcase endgenerate
`endif
endmodule
(* abc_box_id=1008, lib_whitebox, abc9_flop *)
module FDSE_1 (
(* abc_arrival=303 *)
output reg Q,
(* clkbuf_sink *)
input C,
input CE, D, S
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
wire \$currQ ;
reg \$nextQ ;
always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
`ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
// In order to achieve clock-enable behaviour, the current value
// of the sequential output is required which Yosys will
// connect to the special `\$currQ' wire.
// Special signal indicating clock domain
// (used to partition the module so that `abc9' only performs
// sequential synthesis (reachability analysis) correctly on
// one domain at a time)
wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
// Special signal indicating control domain
// (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together)
wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
always @* Q = \$nextQ ;
`else
assign \$currQ = Q;
always @(negedge C) Q <= \$nextQ ;
`endif
endmodule
module RAM32X1D (

4
techlibs/xilinx/synth_xilinx.cc
View file

@ -276,9 +276,9 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("begin")) {
if (vpr)
run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else
run("read_verilog -lib +/xilinx/cells_sim.v");
run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
if (help_mode)
run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");