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Missing endmodule

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Eddie Hung 2019-09-29 21:55:53 -07:00
parent 1123c09588
commit f6203e6bd6
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techlibs/xilinx/abc_model.v
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@ -35,6 +35,7 @@ endmodule
(* abc_box_id = 1000 *)
module \$__ABC_ASYNC (input A, S, output Y);
endmodule
// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
// Necessary since RAMD* and SRL* have both combinatorial (i.e.