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Code Activity
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508 commits

Author SHA1 Message Date
Akash Levy
ed42470d45 Move ignore translate up here and update verificc 2024-05-14 16:02:33 -07:00
Akash Levy
81b542fd31 Updated to support Amba comments and .h files 2024-05-14 13:25:43 -07:00
Akash Levy
667c3375e8 Macro defines don't pass or succeed the same way 2024-05-13 15:53:54 -07:00
Akash Levy
fb182d10d6 Update formats to include .svh 2024-05-13 00:00:49 -07:00
Akash Levy
ba5b12ae0c Don't include source in name 2024-05-11 23:14:39 -07:00
Akash Levy
36f9c50c03 Add mode for nested capital F file 2024-05-11 12:53:33 -07:00
Akash Levy
a7e1dcef12 Move register file to after registering directories, also rename to AUTO-DISCOVER 2024-05-10 12:44:36 -07:00
Akash Levy
fb55287a3b Add SVP extension, log auto-discovery, support gzip in verific 2024-05-10 11:09:22 -07:00
Akash Levy
c7f66737aa Fix Yosys to allow SV again 2024-05-09 06:36:02 -07:00
Akash Levy
da8c1955af Updates from YosysHQ 2024-05-09 05:10:44 -07:00
Akash Levy
8841cc4d76 Copy all info from .f file to hdl_file_sort for better auto-discovery 2024-05-09 04:54:57 -07:00
Akash Levy
b5af9b9a8a Fix SystemVerilog support for .v files 2024-05-09 04:54:00 -07:00
Ethan Mahintorabi
82a4a87c97
Fixes error with vector indicies of the form [2:7] [-12:7] 
Make sure that we correctly adjust the value to align it to a zero
indexed list with lsb = 0

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 20:29:47 +00:00
Akash Levy
47b6738124 Add -auto_discover to import 2024-05-08 04:21:30 -07:00
Ethan Mahintorabi
c039da2ec1
renames variables for more code clairty 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:09:52 +00:00
Ethan Mahintorabi
a2c1b268d9
frontend: Fixes verific import around range order 
Test Case
```
module packed_dimensions_range_ordering (
    input  wire [0:4-1] in,
    output wire [4-1:0] out
);
  assign out = in;
endmodule : packed_dimensions_range_ordering

module instanciates_packed_dimensions_range_ordering (
    input  wire [4-1:0] in,
    output wire [4-1:0] out
);
  packed_dimensions_range_ordering U0 (
      .in (in),
      .out(out)
  );
endmodule : instanciates_packed_dimensions_range_ordering
```

```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = { in[0], in[1], in[2], in[3] };
endmodule

// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = in;
endmodule
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:00:06 +00:00
Akash Levy
3945e6ecff
Merge branch 'YosysHQ:main' into master 2024-04-16 10:59:45 -07:00
Miodrag Milanovic
af94123730 verific: expose library name as module attribute 2024-04-15 17:01:07 +02:00
Akash Levy
6a3bb58d5d Updates from yosys 2024-04-14 18:53:44 -07:00
N. Engelhardt
3d5e23e585
Merge pull request #4302 from YosysHQ/vhdl_2019 
Verific support for VHDL 2019
 2024-04-09 18:25:05 +02:00
Akash Levy
29e9d3ea92 Updates for hiding verific 2024-04-09 07:16:22 -07:00
akash
840cdb415b Update Verific, add to gitmodules, remove unused/GPL features from Makefile 2024-04-08 12:36:08 -07:00
Miodrag Milanovic
f536de0e0e Verific support for VHDL 2019 2024-03-28 13:21:55 +01:00
Akash Levy
dd35d2da23 Modifications 2024-03-21 11:31:43 -07:00
Miodrag Milanovic
4367e176fb code split and cleanup 2024-03-19 09:15:04 +01:00
Miodrag Milanovic
9eebc80170 handle standard types 2024-03-18 10:35:01 +01:00
Miodrag Milanovic
7c09fa572e real number handling and default to string 2024-03-14 10:37:56 +01:00
Miodrag Milanovic
4279cea33a improve handling VHDL constants 2024-03-14 10:37:56 +01:00
Miodrag Milanovic
858eae5572 verific_const: convert VHDL values to RTLIL consts 2024-03-14 10:37:56 +01:00
Miodrag Milanovic
ae7daf99f4 Verific: Add attributes to module instantiation 2024-02-12 09:53:47 +01:00
Ethan Mahintorabi
ff578ecabd
fix formatting 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:23:04 +00:00
Ethan Mahintorabi
bc66dfd9ea
verific: Fixes incorrect aldff inference in verific importer 
The following SV module at HEAD imported with verific,

```systemverilog
    module my_module(
      input logic [4:0] a,
      input logic clk,
      input logic enable,
      output logic [4:0] z
    );

    reg [4:0] pipeline_register;
    always @(posedge clk) begin
      pipeline_register <= enable ? a : pipeline_register;
    end
    assign z = pipeline_register;

    endmodule : my_module

```

results in the following output verilog

```systemverilog
/* Generated by 0.36 */

(* top =  1  *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
  wire [4:0] _0_;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
  input [4:0] a;
  wire [4:0] a;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
  input clk;
  wire clk;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
  input enable;
  wire enable;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
  output [4:0] z;
  wire [4:0] z;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
  \$aldff  #(
    .ALOAD_POLARITY(32'd1),
    .CLK_POLARITY(32'd1),
    .WIDTH(32'd5)
  ) _1_ (
    .AD(5'hxx),
    .ALOAD(1'h0),
    .CLK(clk),
    .D(_0_),
    .Q(z)
  );
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
  \$mux  #(
    .WIDTH(32'd5)
  ) _2_ (
    .A(z),
    .B(a),
    .S(enable),
    .Y(_0_)
  );
endmodule
```

Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.

My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:10:25 +00:00
Miodrag Milanovic
db1de5fe5d verific: add option to skip simplifying complex ports 2024-01-30 16:33:44 +01:00
Miodrag Milanovic
1764c0ee3c Fix verific clocking when no driver exist 2024-01-18 08:47:04 +01:00
Miodrag Milanovic
96fecf0716 Revert "Add attributes to module instantiation" 
This reverts commit 8f207eed1b.
 2023-12-04 16:37:01 +01:00
Miodrag Milanovic
8f207eed1b Add attributes to module instantiation 2023-11-23 11:01:49 +01:00
N. Engelhardt
5fb1264db5 verific: don't try to import attributes from nullptr 2023-11-14 15:05:24 +01:00
N. Engelhardt
93a426cbbf
Merge pull request #4008 from nakengelhardt/mem_libmap_data_attr 
memory_libmap: look for ram_style attributes on surrounding signals
 2023-11-06 16:25:38 +01:00
Miodrag Milanovic
f06d56d224 Handling non-existing location in verific logs 2023-11-03 08:06:16 +01:00
Miodrag Milanovic
4eb18e1f07 change verific log callback api 2023-11-01 08:13:27 +01:00
N. Engelhardt
833b67af80 verific: import attributes on ports 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
 2023-10-20 18:31:41 +02:00
Miodrag Milanovic
d473a207a1 Preserve VHDL architecture name in attribute 2023-10-12 09:17:06 +02:00
Jannis Harder
4ed708836a verific: Use CellBaseName to identify top modules 2023-10-10 11:51:16 +02:00
Miodrag Milanović
a54e6f2d1f
Merge pull request #3984 from YosysHQ/module_hdlname 
verific: save original module name
 2023-10-05 19:41:00 +02:00
Jannis Harder
47a4b790f8 verific: Pass top modules to static elaboration when using hierarchy 2023-10-05 16:51:49 +02:00
Jannis Harder
23b9e61c47 verific: Pass list of top modules to static elaboration 2023-10-05 16:51:49 +02:00
Miodrag Milanovic
268fe92d22 verific: save original module name 2023-10-05 11:22:40 +02:00
Jannis Harder
563a56d9ff verific: Improve interaction between -L, -work and bind statements 2023-10-03 15:52:01 +02:00
Miodrag Milanovic
f193ebdded Verific: add default parameters to modules 2023-09-27 16:57:18 +02:00
Miodrag Milanovic
18855f23ce Set src attribute for verific with full info 2023-09-19 12:00:10 +02:00