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Code Activity
6927 commits 102 branches 53 tags 48 MiB
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1273 commits

Author SHA1 Message Date
Miodrag Milanovic
b3a91d6508 cleanup 2019-08-11 08:37:56 +02:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Clifford Wolf
a469d1a64a
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc 
Add a few comments to document $alu and $lcu
 2019-08-10 09:46:46 +02:00
Eddie Hung
041defc5a6 Reformat so it shows up/looks nice when "help $alu" and "help $alu+" 2019-08-09 12:33:39 -07:00
Eddie Hung
acfb672d34 A bit more on where $lcu comes from 2019-08-09 09:50:47 -07:00
Eddie Hung
5aef998957 Add more comments 2019-08-09 09:48:17 -07:00
Miodrag Milanovic
d51b135e33 Fix CO 2019-08-09 12:37:10 +02:00
Miodrag Milanovic
7a860c5623 Merge remote-tracking branch 'upstream/master' into efinix 2019-08-09 09:46:37 +02:00
Eddie Hung
dae7c59358 Add a few comments to document $alu and $lcu 2019-08-08 10:05:28 -07:00
Eddie Hung
9776084eda Allow whitebox modules to be overwritten 2019-08-07 16:40:24 -07:00
Eddie Hung
675c1d4218 Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
Eddie Hung
cc331cf70d Add test 2019-08-07 16:29:38 -07:00
Eddie Hung
ea8ac8fd74 Remove ice40_unlut 2019-08-07 16:29:38 -07:00
Eddie Hung
6b314c8371 Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER 2019-08-07 16:29:38 -07:00
Eddie Hung
6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214 Merge remote-tracking branch 'origin/master' into eddie/cleanup 2019-08-07 11:11:50 -07:00
Eddie Hung
48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
David Shah
5545cd3c10
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes 
ecp5: Make cells_sim.v consistent with nextpnr
 2019-08-07 15:35:29 +01:00
David Shah
a36fd8582e ecp5: Make cells_sim.v consistent with nextpnr 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:19:31 +01:00
Clifford Wolf
4c49ddf36a
Merge pull request #1249 from mmicko/anlogic_fix 
anlogic : Fix alu mapping
 2019-08-07 12:30:52 +02:00
Eddie Hung
e5be9ff871 Fix spacing 2019-08-06 16:47:55 -07:00
Eddie Hung
c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung
3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Clifford Wolf
023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
Ben Widawsky
7de098ad45 techlibs/intel: Clean up Makefile 
Use GNU make's foreach iterator and remove nonexistent files. Gmake is
already a requirement of the build system.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-08-05 11:22:11 -07:00
Miodrag Milanovic
8a3329871b clock for ram trough gbuf 2019-08-04 12:17:55 +02:00
Miodrag Milanovic
cf96f41c6d Added bram support 2019-08-04 11:46:36 +02:00
Miodrag Milanovic
837cb0a1b9 anlogic : Fix alu mapping 2019-08-03 14:47:33 +02:00
Miodrag Milanovic
6e210f26fa Custom step to add global clock buffers 2019-08-03 14:40:23 +02:00
Miodrag Milanovic
ab98f604fd Initial EFINIX support 2019-08-03 13:10:44 +02:00
Clifford Wolf
f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix 
Fix formatting for msys2 mingw build
 2019-08-02 16:37:57 +02:00
Miodrag Milanovic
28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Eddie Hung
66806085db RST -> RSTBRST for RAMB8BWER 2019-07-29 16:05:44 -07:00
Clifford Wolf
eb663c7579 Merge branch 'ZirconiumX-synth_intel_m9k' 2019-07-25 17:23:48 +02:00
Clifford Wolf
5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads 
intel: Make -noiopads the default
 2019-07-25 17:19:54 +02:00
Eddie Hung
5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff 
xilinx: Fix missing cell name underscore in cells_map.v
 2019-07-25 06:44:17 -07:00
David Shah
ab607e896e xilinx: Fix missing cell name underscore in cells_map.v 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-25 08:19:07 +01:00
Dan Ravensloft
49528ed3bd intel: Make -noiopads the default 2019-07-24 10:38:15 +01:00
Dan Ravensloft
67b4ce06e0 intel: Map M9K BRAM only on families that have it 
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
 2019-07-23 18:11:11 +01:00
David Shah
80884d6f7b ice40: Fix test_dsp_model.sh 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:57 +01:00
David Shah
79f14c7514 ice40/cells_sim.v: Fix sign of J and K partial products 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:33:41 +01:00
David Shah
3c84271543 ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-19 17:13:34 +01:00
Eddie Hung
171cd2ff73 Add tests for all combinations of A and B signedness for comb mul 2019-07-19 08:52:49 -07:00
Eddie Hung
f7753720fe Don't copy ref if exists already 2019-07-19 08:45:35 -07:00
Eddie Hung
43616e1414 Update Makefile too 2019-07-18 14:51:55 -07:00
Eddie Hung
b97fe6e866 Work in progress for renaming labels/options in synth_xilinx 2019-07-18 14:20:43 -07:00
David Shah
9cb0456b6f
Merge pull request #1208 from ZirconiumX/intel_cleanups 
Assorted synth_intel cleanups from @bwidawsk
 2019-07-18 19:04:28 +01:00
Dan Ravensloft
0c999ac2c4 synth_intel: Use stringf 2019-07-18 19:02:23 +01:00