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Author SHA1 Message Date
Akash Levy
80bc373519 carvenetlist: keep cone boundary gate; address review comments
Fix the failing regression test: the single-fanout passthrough removal was
shorting out a cone's only real gate (e.g. a lone $_NOT_ driving an output),
replacing it with a bare wire. That drops the gate entirely (nothing left to
characterize) and, for an inverter, silently drops the inversion, making the
carved cell inequivalent to the RTL. Only short a redundant re-driver whose
input is driven by another in-cone cell; keep a passthrough that reads a
primary input (the cell-under-test's boundary gate).

Also address Greptile review comments:
- fix swapped log_warning arguments in the split-boundary-port diagnostic.
- error out (instead of silently overwriting) when two cell groups rename to
  the same carved module name (e.g. slow_<enc> and fast_<enc> -> <enc>).
- derive pq_speed from the explicit "fast_" base prefix.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 09:13:18 -07:00
Akash Levy
19c28d0e00 Merge branch 'main' into carvenetlist 2026-07-06 08:37:13 -07:00
Akash Levy
63dd7b7ee9
Merge pull request #201 from Silimate/merge5
Merge from upstream
2026-07-06 08:30:57 -07:00
Akash Levy
a2e38e2022 Merge from upstream 2026-07-06 07:47:32 -07:00
Akash Levy
3aa52fb1e5 Pass carvenetlist 2026-07-06 07:44:01 -07:00
Akash Levy
bab0ee6bf8 Speed up opt_* using cut_region with shared_ce 2026-07-06 07:42:47 -07:00
Akash Levy
9d39a82587 Allow sim pass to handle 4-input gates 2026-07-06 07:41:08 -07:00
Akash Levy
b600028644 Reduce verbosity of opt_dff 2026-07-06 07:40:47 -07:00
Akash Levy
7166468c55 Naming improvements 2026-07-06 07:40:14 -07:00
Akash Levy
77cd9e1edc stat bugfix 2026-06-28 20:28:23 -07:00
Akash Levy
d0380bf8f0 New stat 2026-06-28 01:18:21 -07:00
Akash Levy
04a604f9fe Smallfix to simplemap 2026-06-26 11:41:04 -07:00
Akash Levy
e992e76eba
Merge pull request #195 from Silimate/merge3
Merge3
2026-06-25 05:29:55 -07:00
Akash Levy
3783a820ee Merge remote-tracking branch 'upstream' into merge3 2026-06-25 04:51:46 -07:00
Akash Levy
f3b5b8f2c0 Sim count overflow fix pow10 2026-06-25 02:57:14 -07:00
Akash Levy
139caf991c opt_compact_prefix: scope per-sweep clean to module, warn on non-convergence
Address review feedback on the fixpoint loop:
- Scope the per-sweep cleanup to the module under rewrite via
  Pass::call_on_module(..., "clean -purge") instead of running clean over
  the whole design selection. This avoids O(N^2) work across modules and
  keeps untouched modules' dangling cells until their own sweep, matching
  the original single-call behavior.
- Emit a log_warning if a module fails to reach a fixpoint within
  max_sweeps, so silent truncation of compaction is visible.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-24 23:52:30 -07:00
Akash Levy
da947b72d8 opt_compact_prefix fix 3 2026-06-24 22:40:21 -07:00
Akash Levy
9bfe32bffc Reduce port resize to warning 2026-06-24 17:21:38 -07:00
Miodrag Milanovic
fd3ec58055 Remove leftover use of log_id 2026-06-24 08:04:48 +02:00
KrystalDelusion
a07c484ce1
Merge pull request #5981 from YosysHQ/krys/equiv_opt_unknown
equiv_opt: Add ignore-unknown-cells
2026-06-23 19:58:30 +00:00
Miodrag Milanovic
a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Krystine Sherwin
de6aa77dc8
equiv_opt: Add ignore-unknown-cells 2026-06-23 10:54:00 +12:00
nella
3d0c868af0
Merge pull request #5952 from YosysHQ/nella/vector-index
Optimize upto vector indexing (Fix #892).
2026-06-22 09:05:26 +00:00
nella
6ffc938a75
Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup
Add warnings and errors to `sim -r` with VCD code path
2026-06-22 09:02:32 +00:00
Mohamed Gaber
0e7671c1b3 Merge remote-tracking branch 'origin/main' into update_from_upstream 2026-06-21 15:07:32 +03:00
Akash Levy
8cdbd62394 opt_first_fit_alloc: address Greptile review
- pack_lanes: assert elem_w < 32 and pack the full element width instead
  of silently dropping bits >= 31.
- Remove the dead `cell` struct member and its unused assignment in run()
  (every emit helper shadows it with its own local `cell`).
- Decorrelate the pseudo-random bc bits from en (independent mix) so they
  no longer share an LFSR bit (e.g. en[7]/bc[0] for n=8).
- Add purpose comments to fingerprint_dsel and lane_of_bit.

Declined the std::stoi/std::stoll arg-parsing suggestion: it matches the
established convention in sibling passes (opt_argmax, opt_priority_onehot).

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-21 01:21:06 -07:00
Akash Levy
dc995eba98 opt_first_fit_alloc 2026-06-21 00:56:39 -07:00
Mohamed Gaber
4db5fe5f6d
Merge remote-tracking branch 'silimate/main' into update_from_upstream 2026-06-19 00:07:08 +03:00
nella
2195277b5a
Merge pull request #5960 from YosysHQ/nella/latch-infer
proc_dlatch - infer $adlatch (Fix #5910).
2026-06-18 16:50:48 +00:00
nella
c99a037c33
Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745
Fix  `chparam` values are unsigned when using read_verilog frontend
2026-06-18 16:50:22 +00:00
Akash Levy
fe9689eaaf Small update 2026-06-18 05:26:28 -07:00
Akash Levy
db7cfd404d Fix cut_region.h debug 2026-06-18 04:02:52 -07:00
Akash Levy
9df378f8ac opt_carry_select pass 2026-06-18 02:36:29 -07:00
Mohamed Gaber
a4042f69b1
passes/silimate: remove leftover Makefile.inc 2026-06-17 21:14:44 +03:00
Mohamed Gaber
98a1db2756
equiv_opt: support -ignore-unknown-cells 2026-06-17 21:10:02 +03:00
Mohamed Gaber
8267cf87b5
infer_ce: remove pass 2026-06-17 21:01:20 +03:00
Mohamed Gaber
bd7c32f8a6
CMake: Linux fixes + Merge fallout fix 2026-06-16 19:32:45 +03:00
Mohamed Gaber
1d94aa6965
misc: fix unused variable in new main branch merge 2026-06-16 02:14:27 +03:00
Mohamed Gaber
569ab1231b
Merge remote-tracking branch 'silimate/main' into update_from_upstream 2026-06-16 02:02:41 +03:00
Akash Levy
23b021a26b Fix opt_compact_prefix wide packs and opt_priority_onehot max-width test
The tests/silimate suite (which aborted the Run tests CI job) exposed two
issues in the generalized passes:

- opt_compact_prefix: the forward dense pack regressions at 64 and 128 bits
  no longer rewrote. The ConstEval fingerprint was uint64_t-based (capped at
  62 bits) and the per-cone cell cap (max_width*96) was below the O(width^2)
  cell count of a wide pack. The fingerprint now drives whole-width Const
  bit patterns (no width cap) and the cone cap scales quadratically; total
  work stays bounded by the shared walk/eval budgets.

- opt_priority_onehot: the "max-width below lane count" negative test set
  max_width=8 on a 16-lane design expecting no rewrite, but the generalized
  matcher legitimately (and equivalence-provably) rewrites the 8-lane
  sub-region. The test now uses max_width=3 (below min_width 4) to verify
  the width gate suppresses all matching.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-15 12:02:09 -07:00
Akash Levy
1cc985314a Cleanup 2026-06-15 09:09:27 -07:00
nella
a5bdb29d7f Recognise asynchronous set/reset. 2026-06-15 15:44:50 +02:00
Emil J. Tywoniak
6032b064e2 opt_muxtree: optimize for single driver, error on multiple drivers 2026-06-15 15:08:26 +02:00
Akash Levy
83baed6731 Generalize and refactor opt_* passes of Silimate 2026-06-12 16:31:41 -07:00
nella
05805e8b93
Merge pull request #5900 from YosysHQ/nella/arith_tree_improvements
arith_tree improvements
2026-06-12 14:23:10 +00:00
nella
309b7d2496 Verify kogge stone impl. 2026-06-12 14:55:47 +02:00
nella
135c2a4113 Get rid of normalize_to_width. 2026-06-11 01:12:35 +02:00
Mohamed Gaber
0217efb67d
Merge remote-tracking branch 'silimate/main' into update_from_upstream 2026-06-10 20:33:33 +03:00
Mohamed Gaber
d986ee91ac
CMake: integrate silimate additions and extensions
- update CMakeLists.txt to load two new files:
  - SilimateConfig.cmake: sets Silimate configuration options and defaults
  - SilimateVerific.cmake: compiles Verific library, optionally with Silimate modifications
- include silimate tests in test Makefile
2026-06-10 20:27:52 +03:00