136 commits

Author	SHA1	Message	Date
Clifford Wolf	0229d68fc9	Use "opt -fine" in test/vloght/test_mapopt.sh	2014-07-21 21:39:59 +02:00
Clifford Wolf	1241a9fd50	Added "opt_const -fine" and "opt_reduce -fine"	2014-07-21 16:34:16 +02:00
Clifford Wolf	668306d00f	Various improvements in test/vloghtb	2014-07-21 14:40:57 +02:00
Clifford Wolf	3cb61d03f8	Wider range of cell types supported in "share" pass	2014-07-21 12:18:29 +02:00
Clifford Wolf	8836943693	Added yet another resource sharing test case	2014-07-20 21:15:01 +02:00
Clifford Wolf	e9506bb2da	Supercell creation for $div/$mod worked all along, fixed test benches	2014-07-20 18:54:06 +02:00
Clifford Wolf	7a6d578b81	Improved tests/share/generate.py	2014-07-20 17:06:57 +02:00
Clifford Wolf	4af8d84f01	Small fix in tests/vloghtb/run-test.sh	2014-07-20 17:05:20 +02:00
Clifford Wolf	4c38ec1cc8	Added "miter -equiv -flatten"	2014-07-20 15:33:07 +02:00
Clifford Wolf	2e358bd667	Added tests/vloghtb/test_share.sh	2014-07-20 15:33:05 +02:00
Clifford Wolf	6f450d0224	Added tests/share for testing "share" supercell creation	2014-07-20 15:32:59 +02:00
Clifford Wolf	3f9f0c047d	Added tests/vloghtb	2014-07-20 02:19:44 +02:00
Clifford Wolf	297a0962ea	Added SAT-based write-port sharing to memory_share	2014-07-19 15:33:55 +02:00
Clifford Wolf	26f982ac0b	Fixed bug in memory_share feedback-to-en code	2014-07-19 15:32:14 +02:00
Clifford Wolf	e441f07d89	Added translation from read-feedback to en-signals in memory_share	2014-07-18 16:46:40 +02:00
Clifford Wolf	ddb01df42e	Bugfix in tests/memories/run-test.sh	2014-07-18 13:45:25 +02:00
Clifford Wolf	5d9127418b	added tests/memories	2014-07-18 13:25:19 +02:00
Clifford Wolf	ec3a798194	Also simulate unmapped memories in "make test"	2014-07-17 16:53:52 +02:00
Clifford Wolf	9b183539af	Implemented dynamic bit-/part-select for memory writes	2014-07-17 16:49:23 +02:00
Clifford Wolf	5867f6bcdc	Added support for bit/part select to mem2reg rewriter	2014-07-17 13:49:32 +02:00
Clifford Wolf	6d69d4aaa8	Added support for constant bit- or part-select for memory writes	2014-07-17 13:13:21 +02:00
Clifford Wolf	73a345294a	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	2014-07-16 14:08:51 +02:00
Clifford Wolf	964a67ac41	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
Clifford Wolf	3b52121d32	now ignore init attributes on non-register wires in sat command	2014-07-05 11:18:38 +02:00
Clifford Wolf	ee8ad72fd9	fixed parsing of constant with comment between size and value	2014-07-02 06:27:04 +02:00
Clifford Wolf	076182c34e	Fixed handling of mixed real/int ternary expressions	2014-06-25 10:05:36 +02:00
Clifford Wolf	3345fa0bab	Little steps in realmath test bench	2014-06-21 21:43:04 +02:00
Clifford Wolf	df76da8fd7	Added test case for AstNode::MEM2REG_FL_CMPLX_LHS	2014-06-17 21:49:59 +02:00
Clifford Wolf	798ff88855	Improved handling of relational op of real values	2014-06-17 12:47:51 +02:00
Clifford Wolf	88470283c9	Little steps in realmath test bench	2014-06-16 15:21:08 +02:00
Clifford Wolf	398482eced	Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)	2014-06-15 09:39:22 +02:00
Clifford Wolf	a4ec19c25c	Added tests/realmath to "make test"	2014-06-15 09:31:03 +02:00
Clifford Wolf	656685fa31	Improved realmath test bench	2014-06-15 08:48:41 +02:00
Clifford Wolf	11d2add1b9	improved realmath test bench	2014-06-14 21:00:51 +02:00
Clifford Wolf	39eb347c67	progress in realmath test bench	2014-06-14 19:56:22 +02:00
Clifford Wolf	ebe2d73330	added first draft of real math testcase generator	2014-06-14 19:24:01 +02:00
Clifford Wolf	f3b4a9dd24	Added support for math functions	2014-06-14 13:36:23 +02:00
Clifford Wolf	406f86a91e	Added realexpr.v test case	2014-06-14 12:01:17 +02:00
Clifford Wolf	482d9208aa	Added read_verilog -sv options, added support for bit, logic, ... allways_ff, always_comb, and always_latch	2014-06-12 11:54:20 +02:00
Clifford Wolf	3af7c69d1e	added tests for new verilog features	2014-06-07 12:26:11 +02:00
Clifford Wolf	c82db39935	Added tests/simple/repwhile.v	2014-06-06 17:47:20 +02:00
Clifford Wolf	a67cd2d4a2	Progress in Verific bindings	2014-03-17 01:56:00 +01:00
Clifford Wolf	0ac915a757	Progress in Verific bindings	2014-03-14 11:46:13 +01:00
Clifford Wolf	bada3ee815	Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh	2014-03-11 11:59:58 +01:00
Clifford Wolf	4fd1a4c12b	Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)	2014-03-11 11:39:30 +01:00
Clifford Wolf	3c5e973092	Use private namespace in mem_simple_4x1_map	2014-02-21 12:14:38 +01:00
Clifford Wolf	81b3f52519	Added tests/techmap/mem_simple_4x1	2014-02-21 12:06:40 +01:00
Clifford Wolf	772330608a	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	2014-02-19 12:40:49 +01:00
Clifford Wolf	30379ea20d	Added frontend (-f) option to autotest.sh	2014-02-15 15:40:17 +01:00
Clifford Wolf	7664f5d92b	Updated ABC and some related changes	2014-02-13 08:07:08 +01:00