mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-26 13:06:12 +00:00
Code Activity

Added support for bit/part select to mem2reg rewriter

Browse source
This commit is contained in:
Clifford Wolf 2014-07-17 13:49:32 +02:00
parent 6d69d4aaa8
commit 5867f6bcdc
2 changed files with 30 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

21
tests/simple/memory.v
View file

@ -134,3 +134,24 @@ always @(posedge clk) begin
end
endmodule
// ----------------------------------------------------------
module test06(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
(* gentb_constant=0 *) wire rst;
reg [7:0] test [0:7];
integer i;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (i=0; i<8; i=i+1)
test[i] <= 0;
end else begin
test[0][2] <= din[1];
test[0][5] <= test[0][2];
test[idx][3] <= din[idx];
test[idx][6] <= test[idx][2];
test[idx][idx] <= !test[idx][idx];
end
end
assign dout = test[idx];
endmodule