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Implemented dynamic bit-/part-select for memory writes

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This commit is contained in:
Clifford Wolf 2014-07-17 16:49:23 +02:00
parent f1ca93a0a3
commit 9b183539af
2 changed files with 66 additions and 3 deletions
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41
tests/simple/memory.v
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@ -137,7 +137,26 @@ endmodule
// ----------------------------------------------------------
module test06(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
module test06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
(* gentb_constant=0 *) wire rst;
reg [7:0] test [0:7];
integer i;
always @(posedge clk) begin
if (rst) begin
for (i=0; i<8; i=i+1)
test[i] <= 0;
end else begin
test[0][2] <= din[1];
test[0][5] <= test[0][2];
test[idx][3] <= din[idx];
test[idx][6] <= test[idx][2];
test[idx][idx] <= !test[idx][idx];
end
end
assign dout = test[idx];
endmodule
module test06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
(* gentb_constant=0 *) wire rst;
reg [7:0] test [0:7];
integer i;
@ -155,3 +174,23 @@ module test06(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:
end
assign dout = test[idx];
endmodule
// ----------------------------------------------------------
module test07(clk, addr, woffset, wdata, rdata);
input clk;
input [1:0] addr;
input [3:0] wdata;
input [1:0] woffset;
output reg [7:0] rdata;
reg [7:0] mem [0:3];
integer i;
always @(posedge clk) begin
mem[addr][woffset +: 4] <= wdata;
rdata <= mem[addr];
end
endmodule